Abstract: A viewing technology method, system, and non-transitory computer readable medium including a display device associated with a user and at least two drones having an image capturing device, include a drone control circuit configured to control a flight path of the at least two drones such that the drones are separated by the inter-drone distance, a vergence angle determining circuit configured to determine a vergence angle of the pupils of the user relative to the image displayed on the display device, and a image control circuit configured to control a display of the image on the display device according to the vergence angle to cause the image to create a just-noticeable-difference in the image.

Abstract: A viewing technology method, system, and non-transitory computer readable medium including a display device associated with a user and at least two drones having an image capturing device, include a drone control circuit configured to control a flight path of the at least two drones such that the drones are separated by the inter-drone distance, a vergence angle determining circuit configured to determine a vergence angle of the pupils of the user relative to the image displayed on the display device, and a image control circuit configured to control a display of the image on the display device according to the vergence angle to cause the image to create a just-noticeable-difference in the image.

Abstract: Disclosed is a method, system and computer program product to specify an integrated circuit. The integrated circuit includes a hardwired specific logic technology portion and a programmable specific logic technology portion. The method includes generating a hybrid logic network by mapping each uncertain logic function to an abstract programmable logic element implementation thereof and by mapping each known logic function to a technology-independent logic element implementation thereof; simplifying the hybrid logic network using logic synthesis optimizations; mapping the simplified hybrid logic network to a specific technology by mapping the abstract programmable logic element implementation to the specific programmable logic technology and the technology-independent logic element implementation to the specific logic technology; and further includes optimizing the mapped network to meet performance constraints.

Abstract: Disclosed is a method, system and computer program product to specify an integrated circuit. The integrated circuit includes a hardwired specific logic technology portion and a programmable specific logic technology portion. The method includes generating a hybrid logic network by mapping each uncertain logic function to an abstract programmable logic element implementation thereof and by mapping each known logic function to a technology-independent logic element implementation thereof; simplifying the hybrid logic network using logic synthesis optimizations; mapping the simplified hybrid logic network to a specific technology by mapping the abstract programmable logic element implementation to the specific programmable logic technology and the technology-independent logic element implementation to the specific logic technology; and further includes optimizing the mapped network to meet performance constraints.

Abstract: Disclosed is a method, system and computer program product to specify an integrated circuit. The integrated circuit includes a hardwired specific logic technology portion and a programmable specific logic technology portion. The method includes generating a hybrid logic network by mapping each uncertain logic function to an abstract programmable logic element implementation thereof and by mapping each known logic function to a technology-independent logic element implementation thereof; simplifying the hybrid logic network using logic synthesis optimizations; mapping the simplified hybrid logic network to a specific technology by mapping the abstract programmable logic element implementation to the specific programmable logic technology and the technology-independent logic element implementation to the specific logic technology; and further includes optimizing the mapped network to meet performance constraints.

Abstract: Disclosed is a method, system and computer program product to specify an integrated circuit. The integrated circuit includes a hardwired specific logic technology portion and a programmable specific logic technology portion. The method includes generating a hybrid logic network by mapping each uncertain logic function to an abstract programmable logic element implementation thereof and by mapping each known logic function to a technology-independent logic element implementation thereof; simplifying the hybrid logic network using logic synthesis optimizations; mapping the simplified hybrid logic network to a specific technology by mapping the abstract programmable logic element implementation to the specific programmable logic technology and the technology-independent logic element implementation to the specific logic technology; and further includes optimizing the mapped network to meet performance constraints.

Abstract: A method for performing portfolio analysis with a decision model for design automation tools resulting in a design automation tool positioning on a multidimensional decision grid that translates the design automation tool technology into quantified business data needed for making the investment decisions and for optimizing the resource budget within an organization. The decision model is assumed to have been partitioned in two categories: Tool Opportunity Attractiveness (TA) and Tool Implementation Competitiveness (TIC). including the sub-partitions and algorithms. Each partition of the model is assigned to a separate process, each of which may, in general, optimize the resource budget with the result of the tool positioning on the multidimensional decision grid when running independently.

Abstract: An SOI wafer has a device layer of initial thickness that is formed into a set of mesas in the interval between which a temporary layer of polysilicon is deposited to a precisely controlled thickness. This polysilicon is entirely converted in a self-limiting process to an oxide etch stop having a thickness much smaller than the initial thickness. The mesas are thinned by a chemical mechanical polishing technique until the mesa is the same level as the top surface of the new oxide. The etch stop layer of oxide is not removed but serves both as an isolating layer to provide dielectric isolation between mesas in the final circuit and also as a visual gauge to determine the time when the polishing process should stop.

Abstract: Power supply having means for developing a voltage overload signal representing a current overload condition in the power supply and then reducing the output current from the power supply as a result of the voltage overload signal. The voltage overload signal is applied to a servo or error amplifier to cause the error signal therefrom to change in a manner to reduce the power supply output voltage which in turn is fedback to the said amplifier to cause output current foldback.