Abstract: A process for forming chanstops in complementary transistor integrated circuit devices which involves only a single extra masking step yet permits close control of the doping in the chanstops. The process is advantageously used starting with a twin-tub structure for forming CMOS integrated circuit devices.

Abstract: Disclosed are dielectrically isolated high voltage planar devices and methods of fabricating such devices. The devices are designed so that the large electric fields at the junction edges are significantly reduced; thereby permitting a closely packed structure. This concept may be achieved by forming narrow grooves at the junctions and filling with a thermally grown oxide. In a preferred embodiment, the surface of the devices lies in the (110) plane so that the walls of the grooves are perpendicular thereto in the (111) plane. Fabrication includes bonding the semiconductor wafer to a substrate with an oxide layer therebetween and forming grooves through the wafer to the oxide layer for isolation from device to device.