Abstract: An enumeration technique is provided that includes a master/slave embodiment and a half-duplex embodiment.

Abstract: A bit-by-bit error correction technique is disclosed that divides each bit transmission into an acknowledgment phase, an error correction phase, and a transmission phase.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Data is encoded in multi-bit symbols, and the multi-bit symbols are transmitted on a plurality of connectors. The multi-bit symbols may be transmitted by mapping the symbols to a sequence of states of the plurality of connectors, and driving the connectors in accordance with the sequence of states. The timing of the sequence of states is determinable at a receiver at each transition between sequential states. The state of each connector may be defined by polarity and direction of rotation of a multi-phase signal transmitted on the each connector.

Abstract: An intelligent equalization technique is provided for a three-transmitter system in which mid-level transitions are selectively emphasized and de-emphasized to conserve power and reduce data jitter.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N-phase polarity encoded symbols or as packets on differentially driven connectors. A data transfer method comprises encoding data and control signals in a sequence of symbols to be transmitted on a plurality of connectors, and transmitting the sequence of symbols on the plurality of connectors. Each symbol may be transmitted using a combination of a phase state of a first pair of connectors, a polarity of a second pair of connectors, and a selection of at least one undriven connector. Transmission of each symbol in the sequence of symbols may cause a change of state for at least one of the plurality of connectors.

Abstract: An intelligent equalization technique is provided for a three-transmitter system in which mid-level transitions are selectively emphasized and de-emphasized to conserve power and reduce data jitter.

Abstract: A two wire interface is disclosed that serializes messaging signals and GPIO signals into frames transmitted over a transmit pin. The two wire interface is configured to perform flow control by monitoring a voltage for the transmit pin.

Abstract: A multi-modulation scheme is provided that combines pulse-width modulation and phase modulation.

Abstract: A bit-by-bit error correction technique is disclosed that divides each bit transmission into an acknowledgment phase, an error correction phase, and a transmission phase.

Abstract: A two wire interface is disclosed that serializes messaging signals and GPIO signals into frames transmitted over a transmit pin. The two wire interface is configured to perform flow control by monitoring a voltage for the transmit pin.

Abstract: An enumeration technique is provided that includes a master/slave embodiment and a half-duplex embodiment.

Abstract: A multi-modulation scheme is provided that combines pulse-width modulation and phase modulation.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N-phase polarity encoded symbols or as packets on differentially driven connectors. A desired operational mode for communicating between the two devices is determined, an encoder is selected to drive a plurality of connectors communicatively coupling the two devices, and a plurality of drivers is configured to receive encoded data from the encoder and drive the plurality of connectors. Switches may couple outputs of the selected encoder to the plurality of drivers. One or more outputs of another encoder may be caused or forced to enter a high impedance mode.

Abstract: Exemplary embodiments are directed to a coexistence of NFC and wireless power functionalities. A device may include an antenna configured to receive a signal. The device may further include a communication circuit configured to selectively couple to the antenna in a default mode of operation. The device may further include a wireless power circuit configured to selectively couple to the antenna in response to detecting that the signal is provided to power or charge a load.

Abstract: The present invention is directed a digital data interface device for transferring digital presentation data at a high rate over a communication link. The digital data interface device includes a message interpreter, content module and a control module. The digital data interface device may include an MDDI link controller. The digital data interface device can be used to control a peripheral device, such as a camera, bar code reader, image scanner, audio device or other sensor. In one example, a cellular telephone having a camera with an MDDI link and a digital data device interface is provided.

Abstract: Systems and methods of data transmission are disclosed. In an embodiment, at least two transmitters are selectively activated and at least one transmitter is deactivated at a serial interface to transmit data via at least two distinct lines.

Abstract: A method, apparatus, and computer program product embodied on a hardware computer readable storage medium for compensating mismatched delays in at least two signals of a mobile display digital interface (MDDI) system. The method, apparatus, and computer program product embodied on a hardware computer readable storage medium sends a skew calibration packet from a host to a client. The host begins a calibration pattern; then toggling a data signal and a strobe signal at a substantially similar time which strobe signal is used by the client as a clock source. The method, apparatus, and computer program product embodied on a hardware computer readable storage medium also aligns a timing of the strobe signal and the data signal by providing varying delays and resetting the client to an original clock source before a next packet reception.

Abstract: A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

Abstract: The present invention provides systems and methods for adaptive digital data transmission rate control. A digital data transmission system for adaptively transferring packets over a transmission link includes a client device having a bandwidth control module and a host device coupled to the client device over the transmission link. The host device includes one or more bandwidth control registers and a packet builder. The bandwidth control module determines a packet speed and/or size for packets transmitted from the host device to the client device over the transmission link. The bandwidth control registers store the requested packet size and/or rate. The packet builder accesses these registers when transmitting packets to determine the requested packet size and/or rate.

Abstract: The present invention provides systems and methods for implementing cyclic redundancy checks to improve link initialization processing and to exchange system error information. In one aspect, a cyclic redundancy check (CRC) checker is provided that includes a unique pattern detector, a CRC generator, a CRC initializer and a CRC verifier. The CRC checker prepopulates the CRC generator for a unique pattern. Upon receipt of the unique pattern within a data stream received over a digital transmission link, the CRC checker proceeds to check CRCs without the need to queue and store data. In another aspect, a CRC generator system is provided that intentionally corrupts CRC values to transmit system error information. The CRC generator system includes a CRC generator, a CRC corrupter, an error detector and an error value generator. In one example, the digital transmission link is an MDDI link.