Patents by Inventor Georgi Panov
Georgi Panov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10317252Abstract: In accordance with an embodiment, a method of performing a measurement with a capacitive sensor includes generating a periodic excitation signal that includes a series of pulses and smoothing edge transitions of the series of pulses to form a shaped periodic excitation signal that includes a flat region between the smoothed edge transitions. The method further includes providing the shaped periodic excitation signal to a first port of the capacitive sensor and measuring a signal provided by a second port of the capacitive sensor.Type: GrantFiled: March 18, 2016Date of Patent: June 11, 2019Assignee: INFINEON TECHNOLOGIES AGInventors: Andreas Wiesbauer, Christian Ebner, Ernesto Romani, Stephan Mechnig, Georgi Panov, Christian Jenkner, Benno Muehlbacher
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Publication number: 20160305997Abstract: In accordance with an embodiment, a method of performing a measurement with a capacitive sensor includes generating a periodic excitation signal that includes a series of pulses and smoothing edge transitions of the series of pulses to form a shaped periodic excitation signal that includes a flat region between the smoothed edge transitions. The method further includes providing the shaped periodic excitation signal to a first port of the capacitive sensor and measuring a signal provided by a second port of the capacitive sensor.Type: ApplicationFiled: March 18, 2016Publication date: October 20, 2016Inventors: Andreas Wiesbauer, Christian Ebner, Ernesto Romani, Stephan Mechnig, Georgi Panov, Christian Jenkner, Benno Muehlbacher
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Patent number: 9344045Abstract: An amplifier includes a differential input with a positive and a negative input and an analog integrator with a differential integrator input and a differential integrator output. The analog integrator further includes an operational amplifier with a positive operational amplifier input, a negative operational amplifier input, a positive operational amplifier output and a negative operational amplifier output. The differential integrator input is coupled to the differential input. A ternary pulse width modulator includes two modulator inputs coupled to the differential integrator output and two modulator outputs. A first feedback path is coupled between a first of the two modulator outputs and the positive operational amplifier input and a second feedback path is coupled between a second of the two modulator outputs and the negative operational amplifier input. A first divert capacitor is coupled between the positive operational amplifier input and a constant voltage reference.Type: GrantFiled: May 29, 2013Date of Patent: May 17, 2016Assignee: Intel Mobile Communications GmbHInventors: Georgi Panov, Rinaldo Zinke
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Publication number: 20140355790Abstract: An amplifier includes a differential input with a positive and a negative input and an analog integrator with a differential integrator input and a differential integrator output. The analog integrator further includes an operational amplifier with a positive operational amplifier input, a negative operational amplifier input, a positive operational amplifier output and a negative operational amplifier output. The differential integrator input is coupled to the differential input. A ternary pulse width modulator includes two modulator inputs coupled to the differential integrator output and two modulator outputs. A first feedback path is coupled between a first of the two modulator outputs and the positive operational amplifier input and a second feedback path is coupled between a second of the two modulator outputs and the negative operational amplifier input. A first divert capacitor is coupled between the positive operational amplifier input and a constant voltage reference.Type: ApplicationFiled: May 29, 2013Publication date: December 4, 2014Inventors: Georgi PANOV, Rinaldo Zinke
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Publication number: 20140203876Abstract: An amplifier circuit is described comprising a first field effect transistor comprising a first source/drain terminal coupled to a first supply terminal, a second source/drain terminal coupled to an output of the amplifier circuit and a gate terminal; a second field effect transistor comprising a first source/drain terminal coupled to an input of the amplifier circuit, a second source/drain terminal coupled to the gate terminal of the first field effect transistor and a gate terminal; a third field effect transistor comprising a first source/drain terminal coupled to a first bias current source of the amplifier circuit, a second source/drain terminal and a gate terminal coupled to its first source/drain terminal and the gate terminal of the second field effect transistor; a fourth field effect transistor comprising a first source/drain terminal coupled to a second bias current source, a second source/drain terminal coupled to a second supply terminal and a gate terminal coupled to the second source/drain termType: ApplicationFiled: January 23, 2013Publication date: July 24, 2014Applicant: Intel Mobile Communications GmbHInventors: Georgi Panov, Rinaldo Zinke
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Patent number: 8786366Abstract: An amplifier circuit is described comprising a first field effect transistor comprising a first source/drain terminal coupled to a first supply terminal, a second source/drain terminal coupled to an output of the amplifier circuit and a gate terminal; a second field effect transistor comprising a first source/drain terminal coupled to an input of the amplifier circuit, a second source/drain terminal coupled to the gate terminal of the first field effect transistor and a gate terminal; a third field effect transistor comprising a first source/drain terminal coupled to a first bias current source of the amplifier circuit, a second source/drain terminal and a gate terminal coupled to its first source/drain terminal and the gate terminal of the second field effect transistor; a fourth field effect transistor comprising a first source/drain terminal coupled to a second bias current source, a second source/drain terminal coupled to a second supply terminal and a gate terminal coupled to the second source/drain termType: GrantFiled: January 23, 2013Date of Patent: July 22, 2014Assignee: Intel Mobile Communications GmbHInventors: Georgi Panov, Rinaldo Zinke
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Patent number: 8633740Abstract: One embodiment of the present invention relates to a waveform generator that includes a first pair of capacitors, a second pair of capacitors, an op amp and control logic. The op amp has inputs and provides a differential triangular waveform at its outputs as an output signal. The control logic includes capacitor control logic, ramp control logic, reset control logic and charge control logic. The capacitor control logic connects a current pair of the first and second capacitors to the inputs of the op amp. The ramp control logic provides ramp currents to the current pair. The reset control logic resets capacitors of a next pair to selected voltage(s), such as zero. The charge control logic charges the next pair of capacitors, typically after the next pair of capacitors has been driven to the selected voltage(s).Type: GrantFiled: September 8, 2011Date of Patent: January 21, 2014Assignee: Intel Mobile CommunicationsInventor: Georgi Panov
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Patent number: 8581627Abstract: One embodiment of the present invention relates to a level shifter circuit having switchable current mirrors that can be selectively activated and deactivated in a complementary manner to translate differential input signals between logic sides (e.g., to translate a differential input signal received at a low-side to a high-side). A latch is connected to outputs of the switchable current mirrors. The latch is configured to receive a translated output signal from an activated current mirror and drive the other output signal to a complementary value. The latch is also configured to provide the translated output signal to a switching element that deactivates (e.g., turns off) the activated switchable current mirror. Storage of the output signals allows for the current mirrors to remain deactivated until a new input signal is provided to the level shifter circuit, thereby allowing for a reduction in the static power consumption of the level shifter.Type: GrantFiled: August 31, 2011Date of Patent: November 12, 2013Assignee: Intel Mobile Communications GmbHInventor: Georgi Panov
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Publication number: 20130063190Abstract: One embodiment of the present invention relates to a waveform generator that includes a first pair of capacitors, a second pair of capacitors, an op amp and control logic. The op amp has inputs and provides a differential triangular waveform at its outputs as an output signal. The control logic includes capacitor control logic, ramp control logic, reset control logic and charge control logic. The capacitor control logic connects a current pair of the first and second capacitors to the inputs of the op amp. The ramp control logic provides ramp currents to the current pair. The reset control logic resets capacitors of a next pair to selected voltage(s), such as zero. The charge control logic charges the next pair of capacitors, typically after the next pair of capacitors has been driven to the selected voltage(s).Type: ApplicationFiled: September 8, 2011Publication date: March 14, 2013Applicant: Infineon Technologies AGInventor: Georgi Panov
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Publication number: 20130049808Abstract: One embodiment of the present invention relates to a level shifter circuit having switchable current mirrors that can be selectively activated and deactivated in a complementary manner to translate differential input signals between logic sides (e.g., to translate a differential input signal received at a low-side to a high-side). A latch is connected to outputs of the switchable current mirrors. The latch is configured to receive a translated output signal from an activated current mirror and drive the other output signal to a complementary value. The latch is also configured to provide the translated output signal to a switching element that deactivates (e.g., turns off) the activated switchable current mirror. Storage of the output signals allows for the current mirrors to remain deactivated until a new input signal is provided to the level shifter circuit, thereby allowing for a reduction in the static power consumption of the level shifter.Type: ApplicationFiled: August 31, 2011Publication date: February 28, 2013Applicant: Intel Mobile Communications GmbHInventor: Georgi Panov
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Publication number: 20080284393Abstract: Implementations related to low drop output (LDO) circuit arrangements are presented herein.Type: ApplicationFiled: May 14, 2007Publication date: November 20, 2008Applicant: INFINEON TECHNOLOGIES AGInventors: Georgi Panov, Ettore Riccio
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Publication number: 20050195098Abstract: Digital-to-analogue converter for converting a digital input signal into an analogue output signal includes a resistor string with switchable taps, a decoder circuit for connecting or disconnecting the taps in a manner dependent on the digital input signal, and a voltage divider. The voltage divider is operable to generate a divider voltage that divides a voltage difference that occurs between two connectable taps. The analogue output voltage is dependent on the divider voltage generated by the voltage divider.Type: ApplicationFiled: January 14, 2005Publication date: September 8, 2005Inventors: Georgi Panov, Marco Bachhuber