Abstract: A filter comprising an off-chip capacitor is described. The off-chip capacitor may be coupled to a circuit bonding pad. The output terminal of an amplifier may be coupled to the circuit bonding pad by a plurality of conductors insulated from one another over at least a portion between the output terminal and the circuit bonding pad.

Abstract: Techniques to tune a frequency of a sinusoidal signal using devices having controllable signal phase delay times. One implementation may include an input terminal to receive an input signal; a first delay path to selectively receive the input signal; a second delay path to selectively receive the input signal; and a control terminal to control an extent to which the input signal flows through the first delay path and the second delay path.

Abstract: The present invention includes an offset cancellation device having input return loss characteristics suitable for high frequency operation.

Abstract: Disclosed is a transimpedance amplifier comprising a multistage amplifier and a feedback circuit coupled between a single ended input terminal and one of a plurality of differential output terminals of the multistage amplifier. The feedback circuit may control an input voltage at the single input terminal to substantially maintain a set or predetermined transconductance between the single ended input terminal and the differential output terminals.

Abstract: Described are a circuit and system to provide an output signal in response to composite input signal comprising an AC signal component and a DC signal component. An amplifier provides an amplified voltage signal in response to a voltage representative of the composite signal. A filter may provide a filtered voltage signal having a magnitude that is representative of a magnitude of the DC signal component in response to the amplified voltage signal. A DC signal removal circuit may substantially remove at least a portion of the DC signal component from an input terminal in response filtered voltage signal.

Abstract: Disclosed is a transimpedance amplifier comprising a multistage amplifier and a feedback circuit coupled between a single ended input terminal and one of a plurality of differential output terminals of the multistage amplifier. The feedback circuit may control an input voltage a the single input terminal to substantially maintain a set or predetermined transconductance between the single ended input terminal and the differential output terminals.

Abstract: Described are a circuit and system to provide an output signal in response to composite input signal comprising an AC signal component and a DC signal component. An amplifier provides an amplified voltage signal in response to a voltage representative of the composite signal. A filter may provide a filtered voltage signal having a magnitude that is representative of a magnitude of the DC signal component in response to the amplified voltage signal. A DC signal removal circuit may substantially remove at least a portion of the DC signal component from an input terminal in response to the filtered voltage signal.

Abstract: The present invention includes an offset cancellation device having input return loss characteristics suitable for high frequency operation.

Abstract: Techniques to tune a frequency of a sinusoidal signal using devices having controllable signal phase delay times.

Abstract: A charge pump includes a first current source, a second current source, and a current mirror. The first current source is included to set a common mode output voltage of a charge pump core based on a desired common mode input of the charge pump core. The second current source is included to receive the common mode output voltage from the charge pump core. A first input of the current mirror receives a signal from the first current source, and a second input of the current mirror receives a signal from the second current source.

Abstract: There is provided programmability, automatic error correction, flexible inter-path implementation for a bit error rate estimator. The bit error rate estimator uses an initialization configuration for a number of memory elements of a reference pattern generator in such a way as to eliminate the need for an N bit counter. In addition, the bit error rate estimator allows for two error correction options that may be pre-grammed into the system. One option allows the system administrator to monitor the errors in the system and take steps as deemed necessary. Another option generates a new reference pattern if the number of errors detected reaches a predetermined maximum amount. Thus, the bit error rate estimator provides automatic error correction, programmability, and flexible inter-path implementation.