Patents by Inventor Gerald D. Deters

Gerald D. Deters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5920808
    Abstract: A biasing circuit for a power amplifier, for use in a transmitter, that substantially reduces distortion during key-up and thereby reduces key-up time. The power amplifier includes an output transistor and a bias circuit. The bias circuit is applied to all the class AB stages of the power amplifier. The bias circuit provides to the output transistor a first bias level during the preheat period and a second bias level during the transmit period. This first bias level is predetermined to cause the output transistor to reach the steady-state junction temperature achieved by the output transistor during the transmit period (i.e., when transmitting output signals biased with the second bias level). The preheat period ends when this steady-state temperature is reached. Thus, the power amplifier can then transition to a transmit period having already reached the steady-state junction temperature. Because the output transistor is already heated to the steady-state junction temperature, "thermal" distortion (i.e.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: July 6, 1999
    Assignee: Glenayre Electronics, Inc.
    Inventors: David E. Jones, Mark A. Walker, Thomas L. Frederick, Kevin P. Murphy, Gerald D. Deters