Patents by Inventor Gerald G. Pechanek
Gerald G. Pechanek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9400652Abstract: Techniques are described for efficient reordering of data and performing data exchanges within a register file or memory, or in general, any device storing data that is accessible through a set of addressable locations. An address translator is placed in the path of all or a selected set of address busses to a storage device to provide a programmable and selectable means of translating the storage device addresses. An effect of this translation is that the data stored in one pattern may be accessed and stored in another pattern or accessed, processed and stored in another pattern. The address translation operation may be carried out in a single cycle, does not involve the physical movement of data in swap operations, allows data to effectively be ordered more efficiently for algorithmic processing and therefore saves power.Type: GrantFiled: March 20, 2014Date of Patent: July 26, 2016Assignee: Altera CorporationInventors: Edwin F. Barry, Gerald G. Pechanek
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Patent number: 9021236Abstract: Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.Type: GrantFiled: January 9, 2014Date of Patent: April 28, 2015Assignee: Altera CorporationInventors: Gerald G. Pechanek, Stamatis Vassiliadis
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Publication number: 20140173253Abstract: Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units.Type: ApplicationFiled: January 9, 2014Publication date: June 19, 2014Applicant: ALTERA CORPORATIONInventors: Gerald G. Pechanek, Stamatis Vassiliadis
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Publication number: 20130019082Abstract: An array processor includes processing elements arranged in to form a rectangular array. Inter-cluster communication paths are mutually exclusive. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path, thus eliminating half the wiring required for the path. The length of the longest communication path is not directly determined by the overall dimension of the array, as in conventional torus arrays. Rather, the longest communications path is limited by the inter-cluster spacing. Transpose elements of an N×N torus may be combined in clusters and communicate with one another through intra-cluster communications paths. Transpose operation latency is eliminated in this approach. Each PE may have a single transmit port and a single receive port. Thus, the individual PEs are decoupled from the array topology.Type: ApplicationFiled: September 14, 2012Publication date: January 17, 2013Applicant: ALTERA CORPORATIONInventors: Gerald G. Pechanek, Charles W. Kurak, JR.
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Publication number: 20130007331Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.Type: ApplicationFiled: September 12, 2012Publication date: January 3, 2013Applicant: ALTERA CORPORATIONInventors: Gerald G. Pechanek, David Carl Strube, Edwin Frank Barry, Charles W. Kurak, JR., Carl Donald Busboom, Dale Edward Schneider, Nikos P. Pitsianis, Grayson Morris, Edward A. Wolff, Patrick R. Marchand, Ricardo E. Rodriguez, Marco C. Jacobs
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Methods and Apparatus for Efficient Complex Long Multiplication and Covariance Matrix Implementation
Publication number: 20130007421Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: ApplicationFiled: September 13, 2012Publication date: January 3, 2013Applicant: ALTERA CORPORATIONInventors: Gerald G. Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Publication number: 20120173849Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is to required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.Type: ApplicationFiled: March 12, 2012Publication date: July 5, 2012Applicant: ALTERA CORPORATIONInventors: Edwin Frank Barry, Patrick R. Marchand, Gerald G. Pechanek, Larry D. Larsen
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Publication number: 20120124335Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.Type: ApplicationFiled: January 5, 2012Publication date: May 17, 2012Applicant: ALTERA CORPORATIONInventors: Gerald G. Pechanek, David Carl Strube, Edwin Franklin Barry, Charles W. Kurak, JR., Carl Donald Busboom, Dale Edward Schneider, Nikos P. Pitsianis, Grayson Morris, Edward A. Wolff, Patrick R. Marchand, Ricardo E. Rodriguez, Marco C. Jacobs
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Publication number: 20110225224Abstract: Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.Type: ApplicationFiled: May 26, 2011Publication date: September 15, 2011Applicant: ALTERA CORPORATIONInventors: Nikos P. Pitsianis, Gerald G. Pechanek, Ricardo E. Rodriguez
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Publication number: 20110219210Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.Type: ApplicationFiled: May 12, 2011Publication date: September 8, 2011Applicant: ALTERA CORPORATIONInventors: Gerald G. Pechanek, David Carl Strube, Edwin Frank Barry, Charles W. Kurak, JR., Carl Donald Busboom, Dale Edward Schneider, Nikos P. Pitsianis, Grayson Morris, Edward A. Wolff, Patrick R. Marchand, Ricardo E. Rodriguez, Marco C. Jacobs
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Patent number: 7962667Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.Type: GrantFiled: July 12, 2007Date of Patent: June 14, 2011Inventors: Gerald G. Pechanek, David Carl Strube, Edwin Frank Barry, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider, Nikos P. Pitsianis, Grayson Morris, Edward A. Wolff, Patrick R. Marchand, Ricardo E. Rodriguez, Marco C. Jacobs
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Publication number: 20110072250Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.Type: ApplicationFiled: November 30, 2010Publication date: March 24, 2011Applicant: Altera CorporationInventors: Edwin Frank Barry, Patrick R. Marchand, Gerald G. Pechanek, Larry D. Larsen
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Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Publication number: 20100121899Abstract: Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.Type: ApplicationFiled: January 19, 2010Publication date: May 13, 2010Applicant: Altera CorporationInventors: Gerald G. Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Publication number: 20090063724Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.Type: ApplicationFiled: July 12, 2007Publication date: March 5, 2009Inventors: Gerald G. Pechanek, David Carl Strube, Edwin Frank Barry, Charles W. Kurak, JR., Carl Donald Busboom, Dale Edward Schneider, Nikos P. Pitsianis, Grayson Morris, Edward A. Wolff, Patrick R. Marchand, Ricardo E. Rodriguez, Marco C. Jacobs
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Publication number: 20080301414Abstract: Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.Type: ApplicationFiled: August 7, 2008Publication date: December 4, 2008Applicant: Altera CorporationInventors: Nikos P. Pitsianis, Gerald G. Pechanek, Ricardo E. Rodriguez
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Publication number: 20080222333Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.Type: ApplicationFiled: May 14, 2008Publication date: September 11, 2008Applicant: Altera CorporationInventors: Edwin Frank Barry, Patrick R. Marchand, Gerald G. Pechanek, Larry D. Larsen
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Publication number: 20080133892Abstract: Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.Type: ApplicationFiled: July 16, 2007Publication date: June 5, 2008Applicant: ALTERA CORPORATIONInventors: Gerald G. Pechanek, David Carl Strube, Edward A. Wolff, Edwin Frank Barry, Grayson Morris, Carl Donald Busboom, Dale Edward Schneider
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Patent number: 7181730Abstract: Techniques and a set of heuristics are described to perform allocation of the special instruction memory where indirect very long instruction words (VLIW's) are stored for the ManArray family of multiprocessor digital signal processors (DSP). This approach substantially reduces the cost of pre-initializing the contents of VLIWs.Type: GrantFiled: June 21, 2001Date of Patent: February 20, 2007Assignee: Altera CorporationInventors: Nikos P. Pitsianis, Benjamin Strautin, Sanjay Banerjee, Gerald G. Pechanek
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Methods and apparatus for efficient complex long multiplication and covariance matrix implementation
Patent number: 7072929Abstract: A digital signal processor for computing various types of complex multiplication is described. The digital signal processor operates in conjunction with registers, a multiplier, an adder, and a multiplexer The Registers store first and second complex operands. The multiplier simultaneously performs multiplications to produce each combination of products between the real and imaginary terms of the first and second complex operands. The multiplexer selects which produced products are added to or subtracted from each other based on the type of complex multiplication being performed. The adder simultaneously performs additions and subtractions, if necessary, to produce both real and imaginary results depending on whether the type of complex multiplication being performed is a conjugated operation. The registers store the results of the complex multiplication.Type: GrantFiled: November 1, 2001Date of Patent: July 4, 2006Assignee: PTS CorporationInventors: Gerald G. Pechanek, Ricardo Rodriguez, Matthew Plonski, David Strube, Kevin Coopman -
Patent number: 6965991Abstract: A reconfigurable register file system is described. The reconfigurable register file system includes an instruction register for storing an instruction specifying an operational requirement, a reconfigurable register file comprising an odd register file having at least one data read port, and an even register file having at least one data read port. The reconfigurable register file system may further suitably include an execution unit connected to the data read ports of the odd and even register files and port usage control logic connected to the instruction register and the reconfigurable register file to control the odd register file and the even register file port address input so that data read port lines change only as needed to support the operational requirement specified by the instruction.Type: GrantFiled: January 11, 2005Date of Patent: November 15, 2005Assignee: PTS CorporationInventors: Patrick R. Marchand, Gerald G. Pechanek, Edward A. Wolff