Patents by Inventor Gerald L. Cadloni

Gerald L. Cadloni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446241
    Abstract: Several embodiments of memory devices and systems with walking read level calibration are disclosed herein. In one embodiment, a system includes a memory component having at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to perform iterative calibrations of the memory region by determining a first read level offset value during a first calibration. A new base read level test signal is determined based on the first read level offset value. During a second calibration using the new base read level test signal, a second read level offset value is determined.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni
  • Patent number: 10355815
    Abstract: A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Stephen P. Van Aken, Gerald L. Cadloni, John L. Seabury, Robert B. Eisenhuth
  • Patent number: 10242751
    Abstract: An embodiment providing one or more improvements includes a memory loading system and method for at least managing testing of a memory unit using a memory test system and responsive to at least completion of testing and passing the testing, loading non-testing content into the memory unit for delivery to a customer.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: March 26, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Gerald L. Cadloni
  • Patent number: 9985651
    Abstract: Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and determining log-likelihood-ratios (LLRs) based on a number of decisions that correspond to each bin associated with the selected RTSs. Low-density parity-check (LDPC) codewords are decoded using the determined LLRs, and a RTS of the RTSs yielding a least number of failed codewords decoded using the determined LLRs is identified.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: May 29, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chandra C. Varanasi, Gerald L. Cadloni
  • Publication number: 20170264312
    Abstract: Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and determining log-likelihood-ratios (LLRs) based on a number of decisions that correspond to each bin associated with the selected RTSs. Low-density parity-check (LDPC) codewords are decoded using the determined LLRs, and a RTS of the RTSs yielding a least number of failed codewords decoded using the determined LLRs is identified.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Inventors: Chandra C. Varanasi, Gerald L. Cadloni
  • Patent number: 9692449
    Abstract: Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and determining log-likelihood-ratios (LLRs) based on a number of decisions that correspond to each bin associated with the selected RTSs. Low-density parity-check (LDPC) codewords are decoded using the determined LLRs, and a RTS of the RTSs yielding a least number of failed codewords decoded using the determined LLRs is identified.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: June 27, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Chandra C. Varanasi, Gerald L. Cadloni
  • Publication number: 20160269147
    Abstract: A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.
    Type: Application
    Filed: May 20, 2016
    Publication date: September 15, 2016
    Inventors: Bruce A. Liikanen, Stephen P. Van Aken, Gerald L. Cadloni, John L. Seabury, Robert B. Eisenhuth
  • Publication number: 20160197623
    Abstract: Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and determining log-likelihood-ratios (LLRs) based on a number of decisions that correspond to each bin associated with the selected RTSs. Low-density parity-check (LDPC) codewords are decoded using the determined LLRs, and a RTS of the RTSs yielding a least number of failed codewords decoded using the determined LLRs is identified.
    Type: Application
    Filed: March 14, 2016
    Publication date: July 7, 2016
    Inventors: Chandra C. Varanasi, Gerald L. Cadloni
  • Patent number: 9374343
    Abstract: A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: June 21, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Stephen P. Van Aken, Gerald L. Cadloni, John L. Seabury, Robert B. Eisenhuth
  • Patent number: 9306600
    Abstract: Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and determining log-likelihood-ratios (LLRs) based on a number of decisions that correspond to each bin associated with the selected RTSs. Low-density parity-check (LDPC) codewords are decoded using the determined LLRs, and a RTS of the RTSs yielding a least number of failed codewords decoded using the determined LLRs is identified.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Chandra C. Varanasi, Gerald L. Cadloni
  • Publication number: 20150294737
    Abstract: An embodiment providing one or more improvements includes a memory loading system and method for at least managing testing of a memory unit using a memory test system and responsive to at least completion of testing and passing the testing, loading non-testing content into the memory unit for delivery to a customer.
    Type: Application
    Filed: June 3, 2015
    Publication date: October 15, 2015
    Inventor: Gerald L. Cadloni
  • Patent number: 9081717
    Abstract: In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: July 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, Larry J. Koudele, John L. Seabury, Stephen P. VanAken, Guy R. Wagner
  • Patent number: 9082474
    Abstract: An embodiment providing one or more improvements includes a memory loading system and method for at least managing testing of a memory unit using a memory test system and responsive to at least completion of testing and passing the testing, loading non-testing content into the memory unit for delivery to a customer.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: July 14, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Gerald L. Cadloni
  • Publication number: 20150194983
    Abstract: Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and determining log-likelihood-ratios (LLRs) based on a number of decisions that correspond to each bin associated with the selected RTSs. Low-density parity-check (LDPC) codewords are decoded using the determined LLRs, and a RTS of the RTSs yielding a least number of failed codewords decoded using the determined LLRs is identified.
    Type: Application
    Filed: January 6, 2014
    Publication date: July 9, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Chandra C. Varanasi, Gerald L. Cadloni
  • Publication number: 20140380123
    Abstract: In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected.
    Type: Application
    Filed: September 8, 2014
    Publication date: December 25, 2014
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, Larry J. Koudele, John L. Seabury, Stephen P. VanAken, Guy R. Wagner
  • Patent number: 8862969
    Abstract: In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: October 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, Larry J. Koudele, John L. Seabury, Stephen P. Van Aken, Guy R. Wagner
  • Publication number: 20140093076
    Abstract: A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.
    Type: Application
    Filed: December 4, 2013
    Publication date: April 3, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Stephen P. Van Aken, Gerald L. Cadloni, John L. Seabury, Robert B. Eisenhuth
  • Patent number: 8627165
    Abstract: A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for transfer using a multilevel transmission channel. The user data symbols are represented in a digital bitwise form such that each symbol is presented as a plurality of bits and each bit is subject to a different probability of error. An error correction procedure is applied based on the different error probability that is associated with each bit in the plurality. The channel can be configured to support a mosaic tile structure, each tile containing a channel symbol such that a selected tile has a collective error probability that is different from other tiles. Customized coding can be applied to the tile structure to allocate a selected amount of error correction power to the selected tile based on an overall available correction power.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Stephen P. Van Aken, Gerald L. Cadloni, John L. Seabury, Robert B Eisenhuth
  • Publication number: 20130290811
    Abstract: In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected.
    Type: Application
    Filed: June 28, 2013
    Publication date: October 31, 2013
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, Larry J. Koudele, John L. Seabury, Stephen P. Van Aken, Guy R. Wagner
  • Patent number: 8499227
    Abstract: In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: July 30, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, Larry J. Koudele, John L. Seabury, Stephen P. Van Aken, Guy R. Wagner