Patents by Inventor Gerald L. Shipley

Gerald L. Shipley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8165291
    Abstract: A circuit for stabilizing soft bits in a bit stream, the circuit having a first register to receive an initial read of the bit stream, a second register to receive a subsequent read of the bit stream, a comparator to compare the initial read of the bit stream to the subsequent read of the bit stream, a third register to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and an accumulator to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: April 24, 2012
    Assignee: LSI Corporation
    Inventors: Gerald L. Shipley, David A. Castaneda
  • Patent number: 7590624
    Abstract: The present invention is directed to a method of identifying duplicate data elements in large data sets. This involves receiving the data sets. Dividing each data element in the data set into a series of data segments to define data keys. Generating an intermediate value for the each element in the data set using summed values for the data keys. Sorting the data entries using the intermediate values. Sorting the matched intermediate value entries using the data keys. Identifying the duplicate data elements in the data set.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: September 15, 2009
    Assignee: LSI Corporation
    Inventors: Gerald L. Shipley, David A. Castaneda
  • Publication number: 20080068003
    Abstract: A circuit for stabilizing soft bits in a bit stream, the circuit having a first register to receive an initial read of the bit stream, a second register to receive a subsequent read of the bit stream, a comparator to compare the initial read of the bit stream to the subsequent read of the bit stream, a third register to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and an accumulator to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads.
    Type: Application
    Filed: August 24, 2006
    Publication date: March 20, 2008
    Applicant: LSI LOGIC CORPORATION
    Inventors: Gerald L. Shipley, David A. Castaneda