Abstract: In a packet switched communications system an incoming real-time packet is imbedded after the next block of data of the non-real-time packet being transmitted. This object is accomplished by transmitting each packet along with at least a 1-byte trailer which is used to indicate the packet type, whether the current block of non real time data is preempted or whether the current block of non real time data is resumed.

Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprisesmeans for buffering (132) said data packets,means for identifying said buffering means and said data packets in said buffering means,means for queueing (FIG. 15) in storing means (131) said identifying means in a single instruction,means for dequeueing (FIG. 16) from said storing (131) means said identifying means in another single instruction,means for releasing said buffering means,Each instruction comprises up to three operations executed in parallel by said processing means:an arithmetical and logical (ALU) operation on said identifying means,memory operation on said storing means, anda sequence operation.

Abstract: Currently, routing algorithms compute all the available paths in the network, from a source node to a destination node before selecting the optimal route. The route computation is often time and resource consuming. Some paths are not acceptable due to the particular geographical configuration of the network. In the real world, large transport networks are not fully meshed. The present invention is based on the observation that networks are usually built around a hierarchical structure. A set of nodes, interconnected by high throughput lines, are used to build a `Backbone` (401) with a high degree of meshing to allow the redundancy and reliability required by the user. The other nodes or `local` nodes (404) are attached to one or several backbone nodes. It is the network designer responsibility, at the configuration time to define for each node what is its attribution: backbone (402) or local node (404).

Abstract: A packet switching communication system is improved by using a packet header structure which does not require a fixed format. The packet header comprises a chain of 2 byte command/data segments. Each command/data segment contains generic bits and a routing field. One of the generic bits (bit 1) allows the header to be extended with another command/data segment.

Abstract: In a shared memory system, wherein several memory users MU wish access to a plurality of memory banks, a set of high level commands (CREATE, PUT, GET, RELEASE) is provided, to transfer data between a given memory user and the memory banks or another memory user. The high level commands sent by the memory users are built up by memory interfaces MI connected to the memory users, and transmitted through an interconnection network to Packet Memory Command Executors PMCE integrated into each memory bank. The high level commands work with data records identified by Logical Record Addresses (LRA) known by the memory users. During execution of the high level commands by the PMCE, the LRA are translated into physical addresses corresponding to physical address space in the memory banks. The physical address space is created dynamically and released upon need, through the Create or Release Commands.

Abstract: A 3-stage switching system is provided for generating, i.e. finding, reserving and setting, path from one switch entrance port (1) to at least one switch exit port (transmit side) for asynchronously received and buffered data cells. While an Nth cell is being transferred, control means (36) generate a control word including the switch exit port address for cell (N+1)th to be subsequently transferred. Said control word is used to find and reserve a path through the switch on a stage-by-stage basis, and then set said path, if any, using a fed back acknowledgement. The (N+1)th cell path generation is performed during cell N transfer, on a cycle stealing basis.

Abstract: A method of integrating the switching of voice and data between terminals connected to switch adapters. The switching of voice (or more generally synchronous signals) is accomplished by grouping voice samples in a first adapter and bound for the same destination or second adapter into a frame. Connections are then established between the two adapters and the frame is transmitted therethrough. A duplex method can also be set up by transmitting in both directions at the same time once a dual connection between the first and second adapter is established. Hence, a second group of voice samples bound for the first adapter is also formed ina frame. The two frames are then transmitted simultaneously in opposite directions through a dual connection in the switching matrix. Data is switched by storing data in respective memories of respective adapters, wherein each respective memory corresponds to a particular adapter to which the data stored therein is to be sent.

Abstract: A method and apparatus to provide high speed voice/data switching with efficient utilization of available bandwidth and minimal switching delay. More specifically, this invention uses shift registers at each crosspoint of a switching matrix. In each slot position of the register, there is a bit representing the status of an associated crosspoint during a particular time slot. Each slot position of the register represents a different time slot. The status of the crosspoint changes in accordance with the bit that is in a designated slot position during each time slot. During each time slot, at most one bit of data/voice is then transmitted through any given closed crosspoint.

Abstract: A method for providing fault tolerant transmission of electrical signals through a transmission device. A number of redundant signals are transmitted through a transmission device, wherein the number of redundant signals per original signal varies dynamically in accordance with selected conditions. These selected conditions are typical of whether the transmission device, typically a switching network, are in normal or overflow operation. Putatively identical signals at corresponding outputs of the transmission device are then compared and at least one correct output signal is generated therefrom.

Abstract: A protocol for a switching system that establishes multiple parallel paths between users through multiple autonomous switching planes by having a user desiring connection to issue connection requests to each of the switching planes. According to the invention, the user monitors the number of connections that have been successfully completed and if only some of the connections have been completed, because of conflicting requests, it follows a conflict protocol to issue retry requests to the planes on which the connection request was unsuccessful. Each switching plane follows the conflict protocol to respond to the retry request by disconnecting existing connections and completing at most one retried connection request.

Abstract: A multi-plane cross-point switching system in which a communication message from a sender is divided into a plurality of data links that are separately connected through autonomous cross-point switches to the receiver where the links are recombined. The cross-points in each plane are separately set by control messages transmitted along with the separate parts of the divided message.

Abstract: A switching network for selectively connecting at least one input time-division channel on an input link (IL) to at least one output time-division channel on an output link (OL). The network is organized around a closed-loop link (10) on which circulates a multiplex message carrying 512 time-division exchange channels. The input and output links (LE and LS) are respectively multiplexed onto an input multiplex link (IML) and an output multiplex link (OML) which are coupled to the closed loop (10) by a switching module (SM). Each switching module comprises an input buffer (IB), an output buffer (OB) and a local buffer (LB) the addressing of which is selectively controlled by a time slot counter (CRT) or a corresponding pointer memory. So-called "broadcast" connections coupling one input channel to several output channels, and "in-cast" connections coupling several input channels to one output channel, can be established. Each of these connections uses only one exchange channel.

Abstract: The contents of input time-division channels on a closed-loop link (10LO, 10HI) are stored in a memory (173) at the address supplied by an input address counter (IAC) controlled by an incoming timing signal (2MCR). The memory is read out under control of an output address counter (OAC) controlled by an outgoing timing signal (2MCT). Each time interval is divided into one read period and two write periods. Means (186) are provided to select one of the two write periods dependent on the phase relationship between the incoming and outgoing timing signals. The units connected in series by means of the closed-loop link receive a timing signal circulating on a timing loop (15) that is closed by a master timing device (13). Slave timing devices (18) inserted in the timing loop regenerate the timing signals circulating thereon and check same.

Abstract: A modular digital signal processor based on a master-slave architecture has the capability of expanding its processing power by aggregating additional modules in a tree type structure. In such a processor the control functions are subdivided into groups, each for performance in a distinct control unit. One or more of the control units can perform a master function with respect to one or several slaved control units and can itself be a slave to a higher level control unit. The arithmetic data functions of the processor are performed in pipe line multiplier-accumulator units (PMAU), each of which is controlled by, instructions from an associated control unit.

Abstract: An input-output port control subsystem for use with a computer system having separate source and destination buses incorporated therein. Said system including circuitry for controlling operations of said system and said input/output subsystem, said subsystem including a bidirectional input/output bus for transferring data to and from said system, and separate gating means for selectively connecting said source and destination buses to said bidirectional I/O bus. External devices are connected to said bus thru an adaptor unit which is directly connected to said processing system by appropriate control lines. The input/output subsystem is adapted to operate either under programmed I/O control mode thru the central processing system or in cycle steal mode wherein the I/O devices themselves request cycle steal service time on the I/O bus thru their connected adaptor.

Abstract: Two-way links communication capability between time-division multiplexed subsystems is provided via dual time division address and data busses correlated by a recirculating memory having sections respectively associated with the address busses. Addresses on the address busses are recognized by the individual subsystems and further decoded to gate data to and from the busses data according to time slots assigned to terminal devices in the subsystems. The dual bus arrangement provides a full-duplex link in the sense that there is simultaneous communication via the two data busses, one each way.