Abstract: An embodiment generates a composite high speed clock with embedded frame synchronization using simple digital encoding of a high speed reference clock. The high speed reference clock and self-aligned frame synchronization signal are recovered by standard logic gate circuitry. The encoding and decoding circuits are comprised of basic digital logic gates with low propagation delay skew and timing jitter. The encoded clock is easier to transmit from source unit to destination unit over common transmission media (i.e., digital transceivers, amplifiers, splitters, connectors and coaxial cable) because only a single interface is required and because the encoding scheme reduces the composite clock to a minimal transmission bandwidth with constrained waveform harmonic content, relative to a low frequency frame sync with fast rise time that requires a broadband transmission media.

Abstract: A clock recovery circuit for providing clock recovery from a burst signal that is periodically present and absent in a noisy channel. The recovery circuit includes an outer main tracking second-order phase locked loop (PLL) having an analog phase detector, a digital loop filter, and an analog/digital hybrid numerically controlled oscillator (NCO) that operates so that the clock recovery frequency is “frozen” to its last value from the previous burst and the phase detector is disabled during the gaps between data bursts. The NCO is implemented with an inner loop PLL that operates as a high resolution synthesizer having a low internal control bandwidth that preserves VCO phase noise. The outer main loop achieves a higher control bandwidth through direct tuning of the inner loop VCO with the outer loop tuning signal.

Abstract: A reduced power consumption actuator drive circuit that includes separate circuit power paths for different portions of the signal spectrum for applications in which lower frequencies have high amplitudes. The low frequency circuit paths use higher power supply voltages at lower currents and the high frequency circuit paths use lower power supply voltages at higher currents. In one embodiment, the drive circuit drives a nutator that employs a resonating circuit that maintains actuator motion with reduced energy supplied by the power supply.

Abstract: A symbol clock recovery circuit for recovering a symbol clock in an M-ary pulse position modulation (PPM) signal. The recovery circuit includes a largest magnitude comparison circuit that selects a largest magnitude signal value from a group of M signal values aligned with a hypothesis symbol boundary location and the average of that largest magnitude value is compared with a threshold, or with results from other boundary location hypotheses, or with both, to determine the true position of the symbol boundary.

Abstract: An amplitude and phase modulation circuit for modulating an M-ary digital signal having pulses onto a carrier wave for transmission by direct digital synthesis. The modulation circuit includes a digital source that generates a digital signal including pulses representing logical 1s and no pulses representing logical zeros, where a group of M pulses represents a constellation point to be transmitted. The modulation circuit further includes a phase control circuit that provides phase control and an amplitude control circuit that provides pulse width control for the constellation point to be transmitted. A saturated amplifier amplifies the phase and amplitude controlled digital signal and a filter integrates and averages the digital signal to remove noise from the signal so as to convert the digital signal to an analog signal, where the digital source operates to reduce the amplifier power consumption requirements.

Abstract: A plurality of differential encoders encodes a plurality of parallel data bit streams. XOR gates interleave the outputs of the differential encoders forming a single high speed differentially encoded bit stream with a data rate that is the sum of the data rate of the parallel data bit streams. The high speed data stream provides a single differentially encoded input to a differential phase shift keying modulator that generates symbols for a high speed optical communication system.

Abstract: A plurality of differential encoders encodes a plurality of parallel data bit streams. XOR gates interleave the outputs of the differential encoders forming a single high speed differentially encoded bit stream with a data rate that is the sum of the data rate of the parallel data bit streams. The high speed data stream provides a single differentially encoded input to a differential phase shift keying modulator that generates symbols for a high speed optical communication system.

Abstract: A method for ultra wideband (UWB) communication in which UWB pulses encode binary data as either normal or inverted (anti-podal) pulses. In the case of pulses of a carrier signal, each pulse has the carrier signal either inverted or in phase, that is, shifted by 180°, or not. For example, a binary “1” may be encoded as a normal or non-inverted pulse and a binary “0” as an inverted pulse. After each carrier pulse is rectified and filtered, detection is effected using a threshold value of zero, resulting in increased immunity to noise, compared with detection of unidirectional pulses. In one aspect of the invention, data pertaining to multiple communication channels are encoded in time-divided portions of each UWB pulse.

Abstract: A switched low pass filter (18) minimizes transients generated during filter switching events and eliminates active circuit random noise. The switched low pass filter (18) includes a filter input terminal (26) for receiving an input base band signal, and an RC circuit (R1, C1, S1, S2) for receiving the input base band signal and for passing only a filtered portion of the input base band signal depending on a wide, mid or narrow band mode of filter operation. The switched low pass filter (18) also includes a transient reduction circuit (34) in switchable communication with the RC circuit (R1, C1, S1, S2) for minimizing transients and switching events caused by transitioning to the mid and narrow band modes of filter operation.

Abstract: A switched low pass filter (18) minimizes transients generated during filter switching events and eliminates active circuit random noise. The switched low pass filter (18) includes a filter input terminal (26) for receiving an input base band signal, and an RC circuit (R1, C1, S1, S2) for receiving the input base band signal and for passing only a filtered portion of the input base band signal depending on a wide, mid or narrow band mode of filter operation. The switched low pass filter (18) also includes a transient reduction circuit (34) in switchable communication with the RC circuit (R1, C1, S1, S2) for minimizing transients and switching events caused by transitioning to the mid and narrow band modes of filter operation.

Abstract: A phase locked loop (10) for generating a variable output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the variable output frequency signal in response to a tune signal. A phase detector (18) is activable in response to a gating signal (20) to generate an error signal representing a difference between a reference frequency signal and the variable output frequency signal. A loop filter (12) having a filter characteristic, filters the error signal and generates the tune signal. An offset cancellation circuit (22) is coupled to the loop filter (12). In response to an error signal representing phase offset of the phase locked loop (10), the offset cancellation circuit (22) supplies a compensating signal to reduce the phase offset.

Abstract: The present invention provides a phase locked loop (10) for generating a variable output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the variable output frequency signal in response to a tune signal. A feedback frequency divider (16) coupled to the controlled oscillator (14) is operable to generate a divided frequency signal from the variable output frequency signal. A phase detector (18) generates an error signal representing a difference between a reference frequency signal and the divided frequency signal. A sample and hold circuit (22) is activable in response to a gating signal (20) derived from the reference frequency, to sample the error signal and generate a sampled signal. A loop filter (12) filters the sampled signal and generates the tune signal.

Abstract: A phase locked loop (10) for generating an output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the output frequency signal in response to a tune signal. A phase detector (18) generates an error signal representing a difference between a reference frequency signal and the output frequency signal. A loop filter (12) having a filter characteristic, filters the error signal and generates the tune signal. The loop filter (12) includes a bandwidth switching circuit (19) to vary the filter characteristics. A charge cancellation circuit (22) is coupled to the loop filter (12). In response to the error signal, the charge cancellation circuit (22) cancels errors associated with the bandwidth switching circuit.

Abstract: A phase locked loop (10) for generating a variable output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the variable output frequency signal in response to a tune signal. A phase detector (18) is activable in response to a gating signal (20) to generate an error signal representing a difference between a reference frequency signal and the variable output frequency signal. A loop filter (12) having a filter characteristic, filters the error signal and generates the tune signal. An offset cancellation circuit (22) is coupled to the loop filter (12). In response to an error signal representing phase offset of the phase locked loop (10), the offset cancellation circuit (22) supplies a compensating signal to reduce the phase offset.

Abstract: The present invention provides a phase locked loop (10) for generating a variable output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the variable output frequency signal in response to a tune signal. A feedback frequency divider (16) coupled to the controlled oscillator (14) is operable to generate a divided frequency signal from the variable output frequency signal. A phase detector (18) generates an error signal representing a difference between a reference frequency signal and the divided frequency signal. A sample and hold circuit (22) is activable in response to a gating signal (20) derived from the reference frequency, to sample the error signal and generate a sampled signal. A loop filter (12) filters the sampled signal and generates the tune signal.

Abstract: A phase locked loop (10) for generating an output frequency signal. The phase locked loop (10) includes a controlled oscillator (14) to generate the output frequency signal in response to a tune signal. A phase detector (18) generates an error signal representing a difference between a reference frequency signal and the output frequency signal. A loop filter (12) having a filter characteristic, filters the error signal and generates the tune signal. The loop filter (12) includes a bandwidth switching circuit (19) to vary the filter characteristics. A charge cancellation circuit (22) is coupled to the loop filter (12). In response to the error signal, the charge cancellation circuit (22) cancels errors associated with the bandwidth switching circuit.

Abstract: A family of logic circuits using nonhysteretic superconducting quantum interference devices (SQUIDs) connected together to perform various functions using a common operating principle. Each circuit has an output line, first and second power supply lines having first and second voltage states, and input lines that can have one of the two voltage states. A pull-up circuit, having at least one SQUID, is connected between the output line and the first power supply line, and the input lines are coupled to the pull-up circuit in such a manner as to pull the output line to the first voltage state only if the input lines conform with a selected combination of voltage states. A pull-down circuit, also having at least one SQUID, is connected between the output line and the second power supply line, to pull the output line to the second voltage state only when input lines do not conform with the selected combination of voltage states.