Abstract: A method for reconstructing uncorrectable forward error correction (FEC) data includes generating and transcoding a known bit sequence and transmitting a FEC encoded codeword that includes a payload containing the transcoded known bit sequence through a component under test. The method further includes receiving the FEC encoded codeword transmitted via the component under test and determining that the encoded contents of the FEC encoded codeword contains a number of symbol errors that exceeds a predefined threshold. The method also includes utilizing stored scramble seed bits corresponding to an immediately preceding FEC encoded codeword and the transcoded known bit sequence to generate a reconstructed codeword.

Abstract: A method for reconstructing uncorrectable forward error correction (FEC) data includes generating and transcoding a known bit sequence and transmitting a FEC encoded codeword that includes a payload containing the transcoded known bit sequence through a component under test. The method further includes receiving the FEC encoded codeword transmitted via the component under test and determining that the encoded contents of the FEC encoded codeword contains a number of symbol errors that exceeds a predefined threshold. The method also includes utilizing stored scramble seed bits corresponding to an immediately preceding FEC encoded codeword and the transcoded known bit sequence to generate a reconstructed codeword.

Abstract: Conventional test systems can experience issues when attempting to test network nodes or system with realistic high speed forward error correction (FEC) encoded test data. For example, a test system may use a packet data generator to generate eight data streams or lanes of 50 Gigabits per second (Gbps) test data and may then use a multiplexer to combine the eight lanes into a 400 Gbps data stream for transmission using 4-level pulse amplitude modulation (PAM4). To generate a high speed data stream comprising multiple data lanes, the test system may be required to use a master clock or other time synchronization technique to keep the data lanes in sync. Further, to generate an FEC encoded high speed data stream comprising multiple data lanes, the test system may perform FEC encoding across all of the data lanes comprising the high speed data stream, which can make test data modifications difficult afterwards. Hence, issues can arise if a packet data generator lacks capabilities, e.g.

Abstract: According to one method for obtaining information from a hardened forward error correction (FEC) implementation, the method occurs at a test device implemented using at least one processor and at least one memory. The method includes copying data from a data stream that is to be processed by a hardened FEC engine; delaying the copied data while the hardened FEC engine generates corresponding error corrected output using the data; comparing the copied data and the corresponding error corrected output for differences; and generating FEC related metrics based on the comparison.

Abstract: A method for transmit timestamp autocalibration includes generating a calibration pulse for calibrating a transmit timestamp in a transmitting device. The method further includes applying the calibration pulse to a transmit data pipeline in the transmitting device. The method further includes sampling a transmit timestamp when the calibration pulse reaches a timestamp sample triggering location in the transmit data pipeline upstream from an egress point of the transmitting device. The method further includes measuring a latency between a time that the calibration pulse reaches the timestamp sample triggering location and a time that the calibration pulse reaches a location downstream from the timestamp sample triggering location. The method further includes generating an adjusted timestamp based on the measured latency and inserting the adjusted timestamp into a data packet to be transmitted from the transmitting device.

Abstract: A method for evaluating link or component quality using synthetic forward error correction (FEC) includes generating a bit sequence. The method further includes transmitting the bit sequence over a link or through a component under test without adding FEC to the bit sequence. The method further includes receiving a bit sequence transmitted over the link or through the component. The method further includes determining locations of bit errors in the received bit sequence. The method further includes determining locations of synthetic FEC codeword and symbol boundaries in the received bit sequence for the synthetic FEC algorithm against which link or component quality is being evaluated. The method further includes identifying symbol and codeword errors for the synthetic FEC algorithm based on the locations of bit errors in received bit sequence. The method further includes outputting an indication of link or component quality based on the symbol and codeword errors identified for the synthetic FEC algorithm.

Abstract: A method for wide bus pattern matching includes, receiving, in a first clock cycle, a bus width of data from a data bus. The method further includes using pattern compare blocks to compare each n-bit portion of data from the data bus to a plurality of different n-bit pattern portions, n being an integer equal to a smallest boundary in which a pattern can start on the data bus. The method further includes detecting, using a plurality of diagonal detectors, matching pattern portions across the pattern compare blocks that are arranged in a diagonal. The method further includes detecting, using a packet boundary detector, when the matching pattern portions arranged in a diagonal indicate a matching pattern that falls within a set of packet boundaries. The method further includes indicating a positive match when the packet boundary detector indicates that the matching.

Abstract: A method for wide bus pattern matching includes, receiving, in a first clock cycle, a bus width of data from a data bus. The method further includes using pattern compare blocks to compare each n-bit portion of data from the data bus to a plurality of different n-bit pattern portions, n being an integer equal to a smallest boundary in which a pattern can start on the data bus. The method further includes detecting, using a plurality of diagonal detectors, matching pattern portions across the pattern compare blocks that are arranged in a diagonal. The method further includes detecting, using a packet boundary detector, when the matching pattern portions arranged in a diagonal indicate a matching pattern that falls within a set of packet boundaries. The method further includes indicating a positive match when the packet boundary detector indicates that the matching.

Abstract: A method for evaluating link or component quality using synthetic forward error correction (FEC) includes generating a bit sequence. The method further includes transmitting the bit sequence over a link or through a component under test without adding FEC to the bit sequence. The method further includes receiving a bit sequence transmitted over the link or through the component. The method further includes determining locations of bit errors in the received bit sequence. The method further includes determining locations of synthetic FEC codeword and symbol boundaries in the received bit sequence for the synthetic FEC algorithm against which link or component quality is being evaluated. The method further includes identifying symbol and codeword errors for the synthetic FEC algorithm based on the locations of bit errors in received bit sequence. The method further includes outputting an indication of link or component quality based on the symbol and codeword errors identified for the synthetic FEC algorithm.

Abstract: A method for transmit timestamp autocalibration includes generating a calibration pulse for calibrating a transmit timestamp in a transmitting device. The method further includes applying the calibration pulse to a transmit data pipeline in the transmitting device. The method further includes sampling a transmit timestamp when the calibration pulse reaches a timestamp sample triggering location in the transmit data pipeline upstream from an egress point of the transmitting device. The method further includes measuring a latency between a time that the calibration pulse reaches the timestamp sample triggering location and a time that the calibration pulse reaches a location downstream from the timestamp sample triggering location. The method further includes generating an adjusted timestamp based on the measured latency and inserting the adjusted timestamp into a data packet to be transmitted from the transmitting device.

Abstract: A method for transmitting and coherently detecting data transmitted over electrical lanes that experience different amounts of skew includes, at a traffic generation or forwarding device, self calibrating transmit and receive-side components of the traffic generation or forwarding device to account for skew between electrical lanes and setting per-electrical lane delays based on the calibration. Data to be transmitted to a network device is generated. The data to be transmitted is spread, using one of the transmit-side components, over a first number of electrical lanes. The data is multiplexed from the electrical lanes onto a second number of optical lanes, the second number being different from the first number. Data is transmitted to and received from the network device over the optical lanes. Transmitted data is reconstructed from the received data using the receive-side components.

Abstract: The subject matter described herein includes methods, systems, and computer readable media for efficiently scrambling data in high speed communications networks. One exemplary method includes, in a network equipment test device, providing a scrambler for scrambling data to be transmitted to a device under test. Scrambling the data includes separating a scrambling algorithm into a scramble key portion and a data portion. Scrambling the data further includes pre computing and storing the scramble key portion. Scrambling the data further includes precomputing and storing the data portion. Scrambling the data further includes logically combining the precomputed scramble key portion with the precomputed data portion to produce a data bus width scrambled output data. The method further includes transmitting the scrambled output data over a network to the device under test.

Abstract: A method for transmitting and coherently detecting data transmitted over electrical lanes that experience different amounts of skew includes, at a traffic generation or forwarding device, self calibrating transmit and receive-side components of the traffic generation or forwarding device to account for skew between electrical lanes and setting per-electrical lane delays based on the calibration. Data to be transmitted to a network device is generated. The data to be transmitted is spread, using one of the transmit-side components, over a first number of electrical lanes. The data is multiplexed from the electrical lanes onto a second number of optical lanes, the second number being different from the first number. Data is transmitted to and received from the network device over the optical lanes. Transmitted data is reconstructed from the received data using the receive-side components.

Abstract: Methods, systems, and computer readable media for a multi-packet CRC engine are disclosed. According to one aspect, the subject matter described herein includes a system for a multi-packet CRC engine. The system includes an input module for receiving set of bits associated with at least one data packet and identifying packet boundaries within the plurality of bits, multiple CRC pre-calculation blocks (CPBs) that receive from the input module subsets of the set of bits, each subset containing a portion of a packet less than all of a packet, and calculate a CRC value for its respective subset of bits, and an output module for receiving the calculated CRC values from the CPBs and using the calculated CRC values to produce packet-specific CRC values, where the output module is dynamically configurable to combine the calculated CRC values according to the identified packet boundaries to produce packet-specific CRC values.

Abstract: The subject matter described herein includes methods, systems, and computer readable media for efficiently scrambling data in high speed communications networks. One exemplary method includes, in a network equipment test device, providing a scrambler for scrambling data to be transmitted to a device under test. Scrambling the data includes separating a scrambling algorithm into a scramble key portion and a data portion. Scrambling the data further includes pre computing and storing the scramble key portion. Scrambling the data further includes precomputing and storing the data portion. Scrambling the data further includes logically combining the precomputed scramble key portion with the precomputed data portion to produce a data bus width scrambled output data. The method further includes transmitting the scrambled output data over a network to the device under test.

Abstract: Methods, systems, and computer readable media for a multi-packet CRC engine are disclosed. According to one aspect, the subject matter described herein includes a system for a multi-packet CRC engine. The system includes an input module for receiving set of bits associated with at least one data packet and identifying packet boundaries within the plurality of bits, multiple CRC pre-calculation blocks (CPBs) that receive from the input module subsets of the set of bits, each subset containing a portion of a packet less than all of a packet, and calculate a CRC value for its respective subset of bits, and an output module for receiving the calculated CRC values from the CPBs and using the calculated CRC values to produce packet-specific CRC values, where the output module is dynamically configurable to combine the calculated CRC values according to the identified packet boundaries to produce packet-specific CRC values.