Abstract: A system for managing power consumption in a personal computer, specifically peripheral devices including the display and other external devices such as disk drives, CD-ROM drives, modems and the like. A software and hardware architecture is provided for managing the power consumption of peripheral devices through their device drivers and a global event messaging scheme. A set of power events is defined which are delivered to device drivers, through an associated power management handler. Each driver can make the decision as to whether that power event should affect its coupled device's power state.

Abstract: A system for managing power consumption in a personal computer, specifically the CPU and on-board system devices. The present invention manages the power consumption of the CPU and on-board system devices (i.e., core logic) using a global event messaging scheme and an OS-Idle power event and interrupts to provide CPU power management. The CPU's low-power state is implemented such that any or a set of predetermined device interrupts will transition the CPU from low-power state to normal operation which commences at the first instruction of the interrupt handler invoked by the device interrupt. The power consumed by the platform/chipset and controller logic devices, i.e., core logic, influenced by system clocks can be managed by decreasing frequency or stopping the distributed clock(s) altogether when in low-power state.

Abstract: A non-volatile semiconductor memory that is erased in blocks is described. The non-volatile semiconductor memory includes an active block for storing first data and a reserve block for storing second data. The second data is a copy of the first data. The copy is made during a clean-up operation prior to erasure of the active block. The non-volatile semiconductor memory also includes a mapping table for mapping a logical address of an allocation unit to a physical address of a sector within the non-volatile semiconductor memory.

Abstract: A method and apparatus in a computer system for storing data from a volatile cache during a power loss. The apparatus comprises a volatile cache memory and a non-volatile memory. In a preferred embodiment, the non-volatile memory is an electrically erasable programmable read-only memory. The device further comprises power loss detection logic which detects the power loss in the computer system and copy control logic which copies the data contained in the volatile cache memory to the non-volatile memory upon detection of the power loss. The copy control logic is coupled to the volatile cache, the non-volatile memory, and the power loss detection logic. In a preferred embodiment, the copy control logic and the power loss detection logic comprise a microcontroller. The device lastly comprises a power source coupled to the volatile cache memory and the copy control logic, the power source being independent of the computer system power.