Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

Abstract: A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed.

Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

Abstract: A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed.

Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.

Abstract: A system including asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the slave device via a plurality of bidirectional data paths, for example. The master device may control data transfer between the master device and the slave device. More particularly, the master device may adaptively modify transmit characteristics subsequent to adaptively modifying receiver characteristics based upon information received from the slave device via one or more unidirectional data paths.

Abstract: A system including a host coupled to a serially connected chain of memory modules. In one embodiment, at least one of the memory modules includes a cache for storing data stored in a system memory.

Abstract: In a microprocessor module assembly, voltage regulators are integrated into the module and adapted for use with a processor and support electronics likewise mounted on the module. The voltage regulators receive a fixed imput voltage from a motherboard interface and provide modified regulated output voltages to the processor and support electronics. In this manner, the processor module is readily upgradable such that future generations are compatible with a fixed motherboard interface without the need for upgrading voltage regulators on the motherboard. In a preferred embodiment, bulk decoupling capacitance is provided on the processor assembly to stabilize the DC output voltage of the voltage regulators.

Abstract: In a common processor module/motherboard interface, an interface protocol is defined such that a replacement processor module can be recognized by a common motherboard and such that a common processor module can be compatible with multiple motherboards. A module information field stored on a processor module includes status information pertaining to the processor module. When the processor module is coupled to a motherboard, the motherboard downloads the module information field and generates initialization commands for the processor module based on the retrieved module information field. The commands are transferred to the processor module for initialization of the processor.

Abstract: A common motherboard interface accommodates processor modules of different processor architectures. The system comprises an interface for communicating with a processor module inserted at the motherboard. The interface receives an identifier signal from the processor module. The identifier signal identifies the processor module architecture. An architecture selection circuit selectively exchanges processor architecture specific signals with the processor module based on the identifier signal. In this manner, a multiple of processor modules of completely different processor architectures can share a common motherboard, thereby providing a system that can be field-upgraded by processor modules of different architectures, or simply allowing the same motherboard to be employed in two different products of different processor architectures.

Abstract: A low-voltage transmitter and receiver adapted for differential signaling via transmission lines between integrated circuits enables operation at very-high data exchange rates. Such data transmission is achieved in a manner that minimizes reflected energy and minimizes crosstalk between signals propagating over neighboring transmission lines. In achieving optimal transmission characteristics, a bridge circuit is employed to drive the signal. The bridge circuit is connected in series between a pull-up and pull-down resistance, their respective resistance values being programmable to maintain optimal communication rates and quality. The pull-up and pull-down resistors preferably comprise a bank of transistors having source-to-drain resistance values that are binary multiples of each other. The transistors are preferably coupled in parallel with each other and in parallel with a resistor, such that the transistors can be selectively activated by a binary voltage control data word.

Abstract: A voltage-controlled oscillator circuit includes a ring oscillator circuit for generating a signal having a series of pulses. The signal with the series of pulses is ac coupled to a filter circuit which converts the series of pulses into a substantially sinusoidal signal which is substantially symmetrical about the reference potential of the system. The sinusoidal signal is applied to an amplifier which converts the sinusoidal signal into a square wave. Because the square wave is generated as an amplified sine wave, it exhibits a high degree of symmetry, i.e., it has a highly accurate 50-50 duty cycle, which makes it applicable in demanding settings such as serving as a clock signal in a high-speed microprocessor system in which both rising and falling edges of the clock signal are used to synchronize events.

Abstract: A voltage-controlled oscillator circuit includes a ring oscillator circuit for generating a signal having a series of pulses. The signal with the series of pulses is ac coupled to a filter circuit which converts the series of pulses into a substantially sinusoidal signal which is substantially symmetrical about the reference potential of the system. The sinusoidal signal is applied to an amplifier which converts the sinusoidal signal into a square wave. Because the square wave is generated as an amplified sine wave, it exhibits a high degree of symmetry, i.e., it has a highly accurate 50-50 duty cycle, which makes it applicable in demanding settings such as serving as a clock signal in a high-speed microprocessor system in which both rising and falling edges of the clock signal are used to synchronize events.

Abstract: A structure and method for mounting a processor assembly on a mother board and a structure and method for cooling the processor assembly are described. The processor assembly includes a processor circuit board assembly which is located adjacent to a heat sink for removing heat from the circuit board assembly. The heat sink and circuit board assembly are maintained in an upright position with respect to the mother board by a fame mounted on the mother board and/or the computer system chassis. A cover mounted to the top of the frame holds a connector on the processor circuit board assembly in mating contact with a connector on the mother board. The cover also serves to complete an enclosure around the heat sink and processor circuit board assembly. Fans mounted to the frame move air from an intake end of the processor assembly, across cooling fins on the heat sink, to an outlet end of the processor assembly such that a ducted cooling system is provided for the processor assembly.

Abstract: A structure and method for mounting a processor assembly on a mother board and a structure and method for cooling the processor assembly are described. The processor assembly includes a processor circuit board assembly which is located adjacent to a heat sink for removing heat from the circuit board assembly. The heat sink and circuit board assembly are maintained in an upright position with respect to the mother board by a frame mounted on the mother board and/or the computer system chassis. A cover mounted to the top of the frame holds a connector on the processor circuit board assembly in mating contact with a connector on the mother board. The cover also serves to complete an enclosure around the heat sink and processor circuit board assembly. Fans mounted to the frame move air from an intake end of the processor assembly, across cooling fins on the heat sink, to an outlet end of the processor assembly such that a ducted cooling system is provided for the processor assembly.