Patents by Inventor Gerard Bret

Gerard Bret has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040104865
    Abstract: For the coding of information for defining a determined window in a video image, a coding pulse is transmitted in a first of the R,G,B video signals sent to a cathode ray tube monitor. The coding pulse is transmitted within at least one time window associated with a determined frame line, and has a temporal width which corresponds to the width of the window in the video image.
    Type: Application
    Filed: April 8, 2003
    Publication date: June 3, 2004
    Inventors: Christine Masson, Gerard Bret, Frederic Tupin, Olivier Le Briz
  • Patent number: 6449020
    Abstract: A device for regulating the amplitude of a chrominance signal includes a variable gain amplifier having an input receiving a sub-carrier signal, and an output providing a regulated sub-carrier signal. The gain of the amplifier is controlled by two regulation loops. The first regulation loop operates during the duration of the reference burst. The second regulation loop operates during the visible line. Each of these loops include an up/down counter controlled by a clock. A digital-analog converter has an input receiving the output signals from the first and second up/down counters. An output signal from the digital-analog converter is connected to the gain control of the amplifier. The digital-analog amplifier is controlled by another clock.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: September 10, 2002
    Assignee: STMicroelectronics S.A.
    Inventors: Didier Salle, Gérard Bret
  • Patent number: 6433837
    Abstract: The demodulating device for a chrominance signal includes an oscillator with a controlled frequency, and an adjuster for adjusting the oscillator frequency as a function of a charge voltage of a memory capacitor. The adjuster preferably includes a fine adjustment channel to output a first adjustment value that depends on the charge voltage of the memory capacitor, and a coarse adjustment channel to output a second adjustment value. The second adjustment value is modified when the charge voltage of the memory capacitor is not within a given range. The device is used, for example, in integrated SECAM decoders.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: August 13, 2002
    Assignee: STMicroelectronics
    Inventors: Didier Salle, Gérard Bret
  • Patent number: 6151080
    Abstract: The SECAM chrominance signal demodulator includes an oscillator with a controlled frequency, a phase comparator with a first input connected to an oscillator output, a second input to receive a chrominance signal, and an output connected to an input loop of the oscillator. The demodulator further includes a fixed current source, also connected to the loop input, a current mirror to copy a current equal to the sum of the fixed current and a comparator output current in the output branches comprising first and second calibration resistors respectively, in series with a common resistor. Output voltages corresponding to the red and blue components of the chrominance signal are measured at the terminals of the calibration resistors respectively. The demodulator is used in television sets, for example.
    Type: Grant
    Filed: April 8, 1999
    Date of Patent: November 21, 2000
    Assignee: STMicroelectronics S.A.
    Inventors: Didier Salle, Gerard Bret
  • Patent number: 5300834
    Abstract: A circuit with a voltage-controlled variable resistance comprises a MOS transistor (2), one of the main electrodes (S) of which is connected to a common terminal (B), a control voltage (VC) being applied between its control electrode (G) and the common terminal. This circuit comprises a voltage dividing bridge (R1, R2) switched between a first terminal (A) and a common terminal (B) and a follower (6, 4), the input of which receives the output (5) of the divider (R1, R2) and the output (8) is connected to the other main electrode (D) of the MOS transistor; whereby the resistance between the first terminal (A) and the common terminal (B) varies as a function of the control voltage (VC).
    Type: Grant
    Filed: January 30, 1991
    Date of Patent: April 5, 1994
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventor: Gerard Bret
  • Patent number: 5194938
    Abstract: A SECAM decoder comprises an input receiving a chrominance subcarrier (SP); first and second outputs delivering respectively the decoded blue (B2) and red (R2) signals; a first PLL phase demodulator (30) receiving the subcarrier (SP), operative only during the blue lines; a second PLL phase demodulator (31) receiving the subcarrier, operative only during the red lines; a first adder (32) receiving the output signal (B1) of the first demodulator (30) and this same signal delayed by a line period to deliver the decoded blue signal (B2); an adder (33) receiving the output signal (R1) of the second demodulator (31) and this same signal delayed by a line period to deliver the red decoded signal (R2).
    Type: Grant
    Filed: September 17, 1991
    Date of Patent: March 16, 1993
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventors: Michel Imbert, Gerard Bret