Abstract: A data processing system including a memory configured to store confidential data and non-confidential data; a cache memory which is configured to cache data stored in the memory and which comprises a first cache memory region and a second cache memory region; a processing circuit configured to carry out, in a first state of the data processing system, a cryptographic algorithm which operates on the confidential data and on the non-confidential data, wherein the confidential data are cached using the first cache memory region and the non-confidential data are cached using the second cache memory region; and an invalidating circuit configured to invalidate the first cache memory region when the data processing system switches from the first state into a second state.

Abstract: Processor arrangement having a first processor, a second processor, and at least one memory configured to be shared by the first processor and the second processor. The second processor has a memory interface configured to provide access to the at least one memory, and a processor communication interface configured to provide a memory access service to the first processor. The first processor has a processor communication interface configured to use the memory access service from the second processor. The first processor and the second processor use at least one cryptographic mechanism in the context of the memory access service.

Abstract: A first time indication which can be changed by a user and stored in a first memory. Furthermore, in the case of a change in the first time indication which is performed externally to the checking device, the difference between the stored first time indication and the changed first time indication is determined. Furthermore, it is checked whether a predetermined criterion is met by using a trustworthy second time indication, the first time indication and the difference.

Abstract: A data processing system including a memory configured to store confidential data and non-confidential data; a cache memory which is configured to cache data stored in the memory and which comprises a first cache memory region and a second cache memory region; a processing circuit configured to carry out, in a first state of the data processing system, a cryptographic algorithm which operates on the confidential data and on the non-confidential data, wherein the confidential data are cached using the first cache memory region and the non-confidential data are cached using the second cache memory region; and an invalidating circuit configured to invalidate the first cache memory region when the data processing system switches from the first state into a second state.

Abstract: A data processing system comprising a computer chip having a processing circuit and a chip-internal first memory and a chip-external second memory being coupled to the computer chip, wherein the processing circuit is configured to allow execution of computer programs stored in the first memory and to prevent execution of computer programs stored in the second memory when the data processing system is in a first state, and to allow execution of computer programs stored in the second memory when the data processing system is in a second state.

Abstract: Processor arrangement having a first processor, a second processor, and at least one memory configured to be shared by the first processor and the second processor. The second processor has a memory interface configured to provide access to the at least one memory, and a processor communication interface configured to provide a memory access service to the first processor. The first processor has a processor communication interface configured to use the memory access service from the second processor. The first processor and the second processor use at least one cryptographic mechanism in the context of the memory access service.