Patents by Inventor Gerard J. Shaw

Gerard J. Shaw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5166901
    Abstract: A memory cell comprising a memory region of amorphous silicon, such memory region having a first state of substantial electrical nonconductivity programmable to a second state of substantial electrical conductivity in response to an electrical programming signal applied thereto. The memory region is disposed over a metal Schottky contact, such as platinum-silicide (PtSi), formed in a support body. A first barrier layer comprising a refractory metal such as titanium-tungsten (TiW) is disposed between the memory region and Schottky contact. A first input terminal comprising a metal strip conductor, such as aluminum, is disposed over the memory region, with a second refractory metal barrier layer being disposed between the memory region and metal strip conductor. A second input terminal is disposed within the support body.
    Type: Grant
    Filed: February 26, 1991
    Date of Patent: November 24, 1992
    Assignee: Raytheon Company
    Inventors: Gerard J. Shaw, Jok Y. Go, Jay H. Chun, Bruce G. Armstrong, Jerry W. Drake
  • Patent number: 4936928
    Abstract: A semiconductor structure is provided comprising a bulk substrate of semiconductor material having a first-type doping conductivity in a first dopant concentration. A first layer of semiconductor material is epitaxially formed on the substrate, such first layer having the first-type doping conductivity in a second dopant concentration lower than the first concentration. A second layer of semiconductor material is epitaxially formed on the first layer, the second layer having a second-type doping conductivity opposite to the first-type doping conductvity and thereby forming a P-N junction with the first layer. A plurality of regions, comprising semiconductor material having the first-type doping conductivity and extending through the second layer and a predetermined distance into the first layer, are further included for providing electrical isolation between active devices formed in different regions of the second layer.
    Type: Grant
    Filed: April 10, 1989
    Date of Patent: June 26, 1990
    Assignee: Raytheon Company
    Inventors: Gerard J. Shaw, Jok Y. Go
  • Patent number: 4512076
    Abstract: A semiconductor device fabrication process is provided wherein a first window is formed in a first silicon dioxide layer which is disposed over the surface of a silicon layer to expose a first portion of the silicon layer. A doped region is formed in the first portion of a silicon layer exposed by the first window. A second layer of silicon dioxide is deposited over the surface of the first, previously formed, silicon dioxide layer and over the first portion of the silicon layer exposed by the first window. A second window is formed through the first and second silicon dioxide layers to expose a second, different portion of the surface of the silicon layer. A layer of silicon nitride is disposed over the second layer of silicon dioxide and through the second formed window onto the portion of the silicon layer exposed by such second formed window. The surface of the structure is then masked with windows being formed in such mask over the first and second previously exposed portions of the silicon layer.
    Type: Grant
    Filed: December 20, 1982
    Date of Patent: April 23, 1985
    Assignee: Raytheon Company
    Inventors: Deepak Mehrotra, Gerard J. Shaw, Jok Y. Go, Rajni Kant