Abstract: A capacitive amplifier device and technique for mitigating the perturbation within the switchable terminals of a feedback capacitor which is produced by the switching activity performed as part of the device's operation. The capacitive amplifier contains feedback components which can be switched without producing significant kickback or poorly behaved transitions due to the inclusion of at least one dedicated circuit. The dedicated circuit is a kickback limiter circuitry which is connected to a switchable node and is designed to reduce the kickback. The technique for reducing the kickback produced can be achieved by connecting and activating the kickback limiter circuitry.

Abstract: Techniques for interpolating two voltages without loading them and without requiring significant power or additional area are described. The techniques include specific topologies for the buffering amplifiers that offer accuracy by cancelling systematic error sources without relying on high gain, thus simplifying the frequency compensation, and reducing power consumption. This can be achieved by biasing the amplifiers from the load current by an innovative feedback structure, which can remove the need for high impedance nodes inside the amplifiers.

Abstract: A voltage generator circuit can be structured to provide an output voltage having a substantially flat temperature coefficient by use of a circuit loop having transistors and a resistor arranged such that, in operation, current through the resistor has a signed temperature coefficient. The current behavior can be controlled by an output transistor coupled to another transistor, which is coupled to the circuit loop, with this other transistor sized such that, in operation, a voltage of this other transistor has a signed temperature coefficient that is opposite in sign to the signed temperature coefficient of the current through the resistor. Embodiments of voltage generator circuits can also include additional components to trim output voltage, to provide unconditional stability, or other features for the respective voltage generator circuit. In various embodiments, a voltage generator circuit can be implemented as a low drop-out (LDO) voltage regulator.

Abstract: A voltage generator circuit can be structured to provide an output voltage having a substantially flat temperature coefficient by use of a circuit loop having transistors and a resistor arranged such that, in operation, current through the resistor has a signed temperature coefficient. The current behavior can be controlled by an output transistor coupled to another transistor, which is coupled to the circuit loop, with this other transistor sized such that, in operation, a voltage of this other transistor has a signed temperature coefficient that is opposite in sign to the signed temperature coefficient of the current through the resistor. Embodiments of voltage generator circuits can also include additional components to trim output voltage, to provide unconditional stability, or other features for the respective voltage generator circuit. In various embodiments, a voltage generator circuit can be implemented as a low drop-out (LDO) voltage regulator.

Abstract: A common mode reference circuit comprises a divider stage and an output stage. The divider stage includes a first n-channel field effect transistor and p-channel filed effect transistor (NFET/PFET) pair connected in series to a high supply voltage circuit node; and a second NFET/PFET pair connected in series to a low supply voltage circuit node. The output stage includes a first FET connected as a current mirror to a transistor of the first NFET/PFET pair; a second FET connected as a current mirror to a transistor of the second NFET/PFET pair; and a common mode reference output at a series connection from the first FET to the second FET.

Abstract: A common mode reference circuit comprises a divider stage and an output stage. The divider stage includes a first n-channel field effect transistor and p-channel filed effect transistor (NFET/PFET) pair connected in series to a high supply voltage circuit node; and a second NFET/PFET pair connected in series to a low supply voltage circuit node. The output stage includes a first FET connected as a current mirror to a transistor of the first NFET/PFET pair; a second FET connected as a current mirror to a transistor of the second NFET/PFET pair; and a common mode reference output at a series connection from the first FET to the second FET.

Abstract: An analog multiplexer may be used for sampling an input voltage that is capable of having a higher voltage level than an upper supply voltage. The analog multiplexer includes a plurality of input switch circuits and a shorting switch circuit. The plurality of input switch circuits include n-type or p-type laterally diffused field effect transistors (NLDFETs or PLDFETs). At least one of the input switch circuits includes a level shifting switch circuit that is able to sample an input voltage that is greater than the upper supply voltage for the multiplexer. A shorting switch circuit, at an output of the multiplexer, includes a capacitively coupled gate drive circuit and is configured to short a first differential output to a second differential output after the input voltage is sampled.

Abstract: A capacitive gain amplifier circuit amplifies an input signal by a pair of differential amplifier circuits couples in series. The first differential amplifier circuit is reset during an autozero phase while disconnected from the second differential amplifier circuit, and the first and second differential amplifier circuits are connected together in series during a chop phase. A set of feedback capacitors is selectively switched in between respective outputs of the second differential amplifier circuit and respective inputs of the first differential amplifier circuit during the chop phase.

Abstract: The amplifier circuit includes a pair of differential input stages coupled to an output stage where both a selected input stage and an unselected input stage are active with one of either a differential input signal or a reference voltage. A switching network couples a first input differential signal to a first differential input stage and a reference voltage to a second differential input stage when an amplifier input signal is less than a threshold voltage. The switching circuit also couples the second input differential signal to the second differential input stage and the reference voltage to the first differential input stage when the amplifier input signal is greater than the threshold signal.

Abstract: A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase.

Abstract: The amplifier circuit includes a pair of differential input stages coupled to an output stage where both a selected input stage and an unselected input stage are active with one of either a differential input signal or a reference voltage. A switching network couples a first input differential signal to a first differential input stage and a reference voltage to a second differential input stage when an amplifier input signal is less than a threshold voltage. The switching circuit also couples the second input differential signal to the second differential input stage and the reference voltage to the first differential input stage when the amplifier input signal is greater than the threshold signal.

Abstract: An analog multiplexer may be used for sampling an input voltage that is capable of having a higher voltage level than an upper supply voltage. The analog multiplexer includes a plurality of input switch circuits and a shorting switch circuit. The plurality of input switch circuits include n-type or p-type laterally diffused field effect transistors (NLDFETs or PLDFETs). At least one of the input switch circuits includes a level shifting switch circuit that is able to sample an input voltage that is greater than the upper supply voltage for the multiplexer. A shorting switch circuit, at an output of the multiplexer, includes a capacitively coupled gate drive circuit and is configured to short a first differential output to a second differential output after the input voltage is sampled.

Abstract: A capacitive gain amplifier circuit amplifies an input signal by a pair of differential amplifier circuits couples in series. The first differential amplifier circuit is reset during an autozero phase while disconnected from the second differential amplifier circuit, and the first and second differential amplifier circuits are connected together in series during a chop phase. A set of feedback capacitors is selectively switched in between respective outputs of the second differential amplifier circuit and respective inputs of the first differential amplifier circuit during the chop phase.

Abstract: A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase.

Abstract: An output stage of a buffer or an amplifier connected to a switched capacitive load can operate in two phases to perform precharging and fine settling. The precharging and fine settling phases can be synchronized to the switching phases of the switched capacitive load connected to the amplifier. During the precharging phase, the output stage can be disconnected from the prior stages of the amplifier, and the output node of the amplifier can be connected to the switched capacitive load to precharge the capacitive load with the voltage already stored in the output stage. During the fine settling phase, the output stage can be reconnected to the prior stages of the amplifier, and the amplifier nodes can settle and get ready for sampling, which can occur at the end of the fine settling phase.

Abstract: An output stage of a buffer or an amplifier connected to a switched capacitive load can operate in two phases to perform precharging and fine settling. The precharging and fine settling phases can be synchronized to the switching phases of the switched capacitive load connected to the amplifier. During the precharging phase, the output stage can be disconnected from the prior stages of the amplifier, and the output node of the amplifier can be connected to the switched capacitive load to precharge the capacitive load with the voltage already stored in the output stage. During the fine settling phase, the output stage can be reconnected to the prior stages of the amplifier, and the amplifier nodes can settle and get ready for sampling, which can occur at the end of the fine settling phase.

Abstract: Adaptive biasing circuits for input differential pairs of a buffer or an amplifier adapt to autozero currents for discrete pair selection or continuous pair selection. The adaptive biasing circuits include a multistage device including current source and follower devices with a plurality of switches for a two-phase operation: autozero and amplifying phases. During an autozero phase, input differential pairs are isolated from subsequent stages and biasing currents are determined for autozeroing of input offset voltages. During an amplifying phase, both input differential pairs can be coupled to subsequent stages for continuous selection or a selected input differential pair can be coupled to subsequent stages for discrete selection.

Abstract: A multichannel system, including a multiplexer having inputs for a plurality of input channels, and a pre-charge buffer having a plurality of inputs coupled to an input of the multiplexer, and an output coupled to a multiplexer output. The multichannel system may stand alone, or may be coupled to a receiving circuit having an input coupled to an output of the multiplexer. In some instances, the receiving circuit is an analog to digital converter.

Abstract: Adaptive biasing circuits for input differential pairs of a buffer or an amplifier adapt to autozero currents for discrete pair selection or continuous pair selection. The adaptive biasing circuits include a multistage device including current source and follower devices with a plurality of switches for a two-phase operation: autozero and amplifying phases. During an autozero phase, input differential pairs are isolated from subsequent stages and biasing currents are determined for autozeroing of input offset voltages. During an amplifying phase, both input differential pairs can be coupled to subsequent stages for continuous selection or a selected input differential pair can be coupled to subsequent stages for discrete selection.

Abstract: An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.