Abstract: Methods and apparatus are provided for designing a logic circuit using one or more circuit elements having a substantially continuous range of values. A circuit is designed based on a functional description of the circuit and one or more circuit constraints. The circuit is initially designed using a library of discrete circuit element options. The initial circuit design is evaluated to determine whether one or more discrete circuit elements cause the circuit to not satisfy the one or more circuit constraints, such as power, area or timing requirements for the circuit. At least one replacement circuit element is generated that has at least one cell parameter configured such that the at least one replacement circuit element will have a performance characteristic that allows the circuit to satisfy the one or more circuit constraints.

Abstract: A method for manufacturing a semiconductor wafer uses a reticle having a plurality of spaced apart circuit images of identical patterns or images of a common level of a single integrated circuit formed on the reticle and arranged in columns and rows about its central point. At least one column of spaced apart test images are formed outside of and adjacent an outermost column of circuit images. Radiation is projected through the reticle for exposing the patterns on the reticle onto an underlying wafer. A reticle holder having a pair of shutter elements aligned parallel to the columns of images selectively blocks the projection of radiation through the columns of the test images but are exposed in order to form test circuits on the wafer at selected locations.

Abstract: An electronic device, a method of manufacturing an electronic device and an integrated circuit that employs at least one such electronic device to couple first and second circuits together in an isolated fashion. In one embodiment, the electronic device includes a first conductive channel, a second conductive channel and an isolation layer. The isolation layer is formed from and over the first conductive channel, interposing the first conductive channel and the second conductive channel and configured both to isolate the second conductive channel electrically from the first conductive channel and transfer momentum between charge carriers in the first conductive channel and charge carriers in the second conductive channel.

Abstract: An electronic device, a method of manufacturing an electronic device and an integrated circuit that employs at least one such electronic device to couple first and second circuits together in an isolated fashion. In one embodiment, the electronic device includes a first conductive channel, a second conductive channel and an isolation layer. The isolation layer is formed from and over the first conductive channel, interposing the first conductive channel and the second conductive channel and configured both to isolate the second conductive channel electrically from the first conductive channel and transfer momentum between charge carriers in the first conductive channel and charge carriers in the second conductive channel.

Abstract: A bond pad support structure for a semiconductor device comprises at least two metal layers subjacent an uppermost passivation layer on the device. An opening through the passivation layer exposes a top surface of a top metal layer. A metal feature is formed in an insulating layer, disposed between the two metal layers, and divides the insulating layer into a plurality of discrete sections. The metal feature includes a plurality of intersecting metal-filled recesses that interconnect the two metal layers. At least a portion of the metal feature is disposed within a cross-sectional area defined as a perimeter of a periphery of the opening.

Abstract: A method for manufacturing a semiconductor wafer uses a reticle having a plurality of spaced apart circuit images of identical patterns or images of a common level of a single integrated circuit formed on the reticle and arranged in columns and rows about its central point. At least one column of spaced apart test images are formed outside of and adjacent an outermost column of circuit images. Radiation is projected through the reticle for exposing the patterns on the reticle onto an underlying wafer. A reticle holder having a pair of shutter elements aligned parallel to the columns of images selectively blocks the projection of radiation through the columns of the test images but are exposed in order to form test circuits on the wafer at selected locations.