Patents by Inventor Gerd Schuppener
Gerd Schuppener has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10483609Abstract: A digital system has a dielectric core waveguide that is formed within a multilayer substrate. The dielectric waveguide has a longitudinal dielectric core member formed in the core layer having two adjacent longitudinal sides each separated from the core layer by a corresponding slot portion formed in the core layer The dielectric core member has the first dielectric constant value. A cladding surrounds the dielectric core member formed by a top layer and the bottom layer infilling the slot portions of the core layer. The cladding has a dielectric constant value that is lower than the first dielectric constant value.Type: GrantFiled: June 6, 2017Date of Patent: November 19, 2019Assignee: Texas Instruments IncorporatedInventors: Robert Floyd Payne, Gerd Schuppener, Juan Alejandro Herbsommer
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Publication number: 20190267979Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: ApplicationFiled: May 13, 2019Publication date: August 29, 2019Inventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
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Patent number: 10291218Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: GrantFiled: June 29, 2018Date of Patent: May 14, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
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Publication number: 20190109362Abstract: An interposer that acts as a buffer zone between a transceiver IC and a dielectric waveguide interconnect is used to establish two well defined reference planes that can be optimized independently. The interposer includes a block of material having a first interface region to interface with an antenna coupled to an integrated circuit (IC) and a second interface region to interface to the dielectric waveguide. An interface waveguide is formed by a defined region positioned within the block of material between the first interface region and the second interface region.Type: ApplicationFiled: September 19, 2018Publication date: April 11, 2019Inventors: Baher Haroun, Juan Alejandro Herbsommer, Gerd Schuppener, Swaminathan Sankaran
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Publication number: 20190097593Abstract: An offset cancellation circuit and method are provided where successive stages of cascaded amplifiers are operated in a saturated state. Biasing is provided, by a feedback amplifier, connected in a feedback loop for each cascaded amplifier, so as to be responsive, in a non-saturated state, to the input of an associated amplifier stage operating in the saturated state.Type: ApplicationFiled: September 26, 2017Publication date: March 28, 2019Inventors: Jikai Chen, Gerd Schuppener, Yanli Fan
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Publication number: 20180309431Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: ApplicationFiled: June 29, 2018Publication date: October 25, 2018Inventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
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Patent number: 10033365Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: GrantFiled: May 18, 2017Date of Patent: July 24, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
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Patent number: 9780768Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: GrantFiled: October 30, 2015Date of Patent: October 3, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
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Publication number: 20170271736Abstract: A digital system has a dielectric core waveguide that is formed within a multilayer substrate. The dielectric waveguide has a longitudinal dielectric core member formed in the core layer having two adjacent longitudinal sides each separated from the core layer by a corresponding slot portion formed in the core layer The dielectric core member has the first dielectric constant value. A cladding surrounds the dielectric core member formed by a top layer and the bottom layer infilling the slot portions of the core layer. The cladding has a dielectric constant value that is lower than the first dielectric constant value.Type: ApplicationFiled: June 6, 2017Publication date: September 21, 2017Inventors: Robert Floyd Payne, Gerd Schuppener, Juan Alejandro Herbsommer
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Publication number: 20170257087Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: ApplicationFiled: May 18, 2017Publication date: September 7, 2017Inventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
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Patent number: 9711837Abstract: A multichannel dielectric wave guide includes a set of dielectric core members that have a length and a cross section shape that is approximately rectangular, The core members have a first dielectric constant value. A cladding surrounds the set of dielectric core members and has a second dielectric constant value that is lower than the first dielectric constant.Type: GrantFiled: April 2, 2013Date of Patent: July 18, 2017Assignee: Texas Instruments IncorporatedInventors: Robert Floyd Payne, Juan Alejandro Herbsommer, Gerd Schuppener
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Patent number: 9705174Abstract: A digital system has a dielectric core waveguide that is formed within a multilayer substrate. The dielectric waveguide has a longitudinal dielectric core member formed in the core layer having two adjacent longitudinal sides each separated from the core layer by a corresponding slot portion formed in the core layer The dielectric core member has the first dielectric constant value. A cladding surrounds the dielectric core member formed by a top layer and the bottom layer infilling the slot portions of the core layer. The cladding has a dielectric constant value that is lower than the first dielectric constant value.Type: GrantFiled: November 26, 2014Date of Patent: July 11, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Robert Floyd Payne, Gerd Schuppener, Juan Alejandro Herbsommer
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Publication number: 20170126219Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Mohammad ELBADRY, Robert Floyd PAYNE, Gerd Schuppener
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Patent number: 9601819Abstract: A dielectric wave guide (DWG) has a dielectric core member that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the DWG is configured for mating with a second DWG having a matching non-planar shaped mating end. A deformable material is disposed on the surface of the mating end of the DWG, such that when mated to a second DWG, the deformable material fills a gap region between the mating ends of the DWG and the second DWG.Type: GrantFiled: April 1, 2013Date of Patent: March 21, 2017Assignee: Texas Instruments IncorporatedInventors: Juan Alejandro Herbsommer, Gerd Schuppener, Robert Floyd Payne
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Patent number: 9570788Abstract: A communication cable includes one or more conductive elements surrounded by a dielectric sheath. The sheath member has a first dielectric constant value. A dielectric core member is placed longitudinally adjacent to and in contact with an outer surface of the sheath member. The core member has a second dielectric constant value that is higher than the first dielectric constant value. A cladding surrounds the sheath member and the dielectric core member. The cladding has a third dielectric constant value that is lower than the second dielectric constant value. A dielectric wave guide is formed by the dielectric core member surrounded by the sheath and the cladding.Type: GrantFiled: June 29, 2015Date of Patent: February 14, 2017Assignee: Texas Instruments IncorporatedInventors: Robert Floyd Payne, Juan Alejandro Herbsommer, Gerd Schuppener
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Patent number: 9515367Abstract: A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the metallic waveguide and down to contact the multilayer substrate. A pinnacle of the tapered end is coupled to the ground plane element, and the bottom side of the metallic waveguide is in contact with the multiplayer substrate and coupled to the microstrip line.Type: GrantFiled: November 12, 2015Date of Patent: December 6, 2016Assignee: Texas Instruments IncorporatedInventors: Juan Alejandro Herbsommer, Robert Floyd Payne, Gerd Schuppener, Baher Haroun
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Patent number: 9373878Abstract: A communication cable includes a dielectric wave guide (DWG) that has a dielectric core member that has a first dielectric constant value and a cladding surrounding the dielectric core member that has a second dielectric constant value that is lower than the first dielectric constant. An RJ45 compatible connector is attached to a mating end of the DWG. The RJ45 connector is configured to retain a complimentary coupling mechanism on a mating end of a second DWG.Type: GrantFiled: April 1, 2013Date of Patent: June 21, 2016Assignee: Texas Instruments IncorporatedInventors: Gerd Schuppener, Juan Alejandro Herbsommer, Robert Floyd Payne
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Patent number: 9350063Abstract: A dielectric wave guide (DWG) has a dielectric core member having that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the DWG is configured in a non-planer shape for mating with a second DWG having a matching non-planar shaped mating end.Type: GrantFiled: April 1, 2013Date of Patent: May 24, 2016Assignee: Texas Instruments IncorporatedInventors: Juan Alejandro Herbsommer, Gerd Schuppener, Robert Floyd Payne
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Patent number: 9312591Abstract: A dielectric wave guide (DWG) has a longitudinal dielectric core member. The core member has a first dielectric constant value. A cladding surrounds the dielectric core member and has a second dielectric constant value that is lower than the first dielectric constant. A portion of the DWG is configured as a corner having a radius. A conductive layer formed on an outer radius of the corner.Type: GrantFiled: April 1, 2013Date of Patent: April 12, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Juan Alejandro Herbsommer, Gerd Schuppener, Robert Floyd Payne
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Patent number: 9300024Abstract: A system includes an electronic device coupled to a mating end of a dielectric wave guide (DWG). The electronic device has a multilayer substrate that has an interface surface configured for interfacing to the mating end of the DWG. A conductive layer is etched to form a dipole antenna disposed adjacent the interface surface. A reflector structure is formed in the substrate adjacent the dipole antenna opposite from the interface surface. A set of director elements is embedded in the mating end of the DWG. Specific spacing is maintained between the dipole antenna and the set of director elements.Type: GrantFiled: April 2, 2013Date of Patent: March 29, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gerd Schuppener, Juan Alejandro Herbsommer, Robert Floyd Payne