Abstract: A bootstrapped switch circuit coupled to a timing circuit. The bootstrapped switch circuit comprises a charge pump coupled to the timing circuit. The bootstrapped switch circuit also comprises a logic circuit coupled to the output of the charge pump and the timing circuit. The logic circuit is capable of generating multiple control signals which can independently control the turn-on of switches in the voltage path between the inputs and outputs of the bootstrapped switch circuit.

Abstract: A charge pump is connected between a source and a body of the switch. Such a configuration avoids a condition in which the body diode opens for negative drain-to-source voltage (Vds) across the switch. Such a configuration also avoids a condition in which the switch control circuit generates control signals referenced to a body potential rather than a source potential, thereby allowing the switch to reliably turn off even for negative Vds. An additional gain stage ensures that the switch can be properly turned on. The techniques can be used to generate switches that enable highly linear processing of bipolar differential signals even far outside of the supply range.

Abstract: Techniques are described through which continuous gapless voltage measurements can be synchronized between devices with independent clock sources on an asynchronous bus by slightly adjusting a speed of a local clock source for a period of time. Also, a read-out technique is described through which the synchronous measurements can be read out in a coherent way. These techniques can allow a high-accuracy time-average of the battery cell voltage (or fuel cell voltage) to be reconstructed, while allowing the same results to be synchronous across an entire battery stack, for use in instantaneous voltage/current diagnostics or calculations.

Abstract: A circuit may increase input transconductance. An input stage may include a field effect transistor (FET) that has a gate, source, drain, and body terminal. An amplifier may generate an amplified version of the input voltage received that is applied to the body terminal of the FET. Application of the amplified version to the body terminal of the FET may increase the transconductance of the FET compared to what it would be in the same circuit without the amplified version being applied to the body terminal of the FET.

Abstract: A bootstrapped switch circuit capable of operating at input signals from far below the negative supply rail to far beyond the positive supply rail may include (a) a switch having a first terminal coupled to an input terminal, a second terminal coupled to an output terminal, and a control terminal; (b) a charge pump coupled to one or more clock signals and isolated from a timing circuit via a first capacitor and a second capacitor, the charge pump generating an output voltage; and (c) a logic circuit coupled to one or more clock signals and isolated from the timing control circuit via a third capacitor and a fourth capacitor, wherein the logic circuit provides a control signal to the control terminal of the switch that is derived from the output voltage of the charge pump.

Abstract: A system for and method of providing a signal proportional to the absolute temperature of a semiconductor junction is provided. The system comprises: a preprocessing stage configured and arranged so as to process a signal from the semiconductor junction so as to produce a preprocessed signal including a resistance error term; and a temperature to voltage converter stage for converting the preprocessed signal to a voltage proportional to absolute temperature representing the absolute temperature of the semiconductor junction; wherein the system is configured and arranged so as to remove the resistance error term so as to produce a resistance error free signal representative of the semiconductor junction temperature.

Abstract: A method and an ADC circuit use multiple SD modulations on an analog value and apply digital post-processing of the pulse density modulation (PDM) streams from the SD modulations obtaining a higher resolution in the digital output value for a given oversampling ratio. SD ADC does not face the constraint of conversion time doubling for each additional bit of resolution. In one implementation, an SD ADC includes conversions in SD phase and resolution-boosting phase. During SD phase, MSBs of the digital output value are generated from the sampled analog value using a first SD conversion. At the end of SD phase, the sampled analog value is reduced to “residual quantization error,” which remains in a capacitor of an integrator of SD ADC. In resolution-boosting phase, the LSBs of the digital output value are generated from residual quantization error using a second SD conversion that provides at least the LSBs.

Abstract: A bootstrapped switch circuit capable of operating at input signals from far below the negative supply rail to far beyond the positive supply rail may include (a) a switch having a first terminal coupled to an input terminal, a second terminal coupled to an output terminal, and a control terminal; (b) a charge pump coupled to one or more clock signals and isolated from a timing circuit via a first capacitor and a second capacitor, the charge pump generating an output voltage; and (c) a logic circuit coupled to one or more clock signals and isolated from the timing control circuit via a third capacitor and a fourth capacitor, wherein the logic circuit provides a control signal to the control terminal of the switch that is derived from the output voltage of the charge pump.

Abstract: Methods and systems for sampling a differential signal. The sampling circuit includes a differential input and a differential output. A logic control block, which is powered by VDD and VSS sources, controls the state of switches used to sample and store differential signals. The logic control block is AC coupled to the switches. The sampling circuit is configured to sample a common mode voltage at the differential input of a level that exceeds that of the VDD and VSS sources.

Abstract: A method and an ADC circuit use multiple SD modulations on an analog value and apply digital post-processing of the pulse density modulation (PDM) streams from the SD modulations obtaining a higher resolution in the digital output value for a given oversampling ratio. SD ADC does not face the constraint of conversion time doubling for each additional bit of resolution. In one implementation, an SD ADC includes conversions in SD phase and a resolution-boosting phase. During SD phase, MSBs of the digital output value are generated from the sampled analog value using a first SD conversion. At the end of SD phase, the sampled analog value is reduced to “residual quantization error,” which remains in a capacitor of an integrator of SD ADC. In resolution-boosting phase, the LSBs of the digital output value are generated from residual quantization error using a second SD conversion that provides at least the LSBs.

Abstract: A method and a circuit achieve fully isolated sampling of bipolar differential voltage signals. The isolated sampling network is suitable for applications in which sampling signals far outside of the supply voltages are desired. A sampling network of the present invention may sample a differential signal between voltages ?VDSMAX and VDSMAX, even with common mode voltages that exceed the supply voltage (e.g., an input stage of an ADC). The bipolar isolated input sampling network may include a polarity comparator and sampling switches that operate as rectifiers. Rectification ensures that a unipolar sampling network needs only to sample signals of predetermined voltage levels.

Abstract: Methods and systems for a differential correlated double sampling (CDS) switched capacitor integrator circuit. The circuit includes a differential amplifier that has a differential input and a differential output. There is a first feedback path between the negative output node and the positive input node, and a second feedback path between the positive output node and the negative input node. Each feedback path includes an integration capacitor and at least one switch that has a parasitic capacitance. A first capacitive element is coupled between the negative input node and the negative output node, and a second capacitive element is coupled between the positive input node and the positive output node. Each capacitive element is configured to cancel the parasitic capacitance of its corresponding feedback path.

Abstract: A system for and method of providing a signal proportional to the absolute temperature of a semiconductor junction is provided. The system comprises: a preprocessing stage configured and arranged so as to process a signal from the semiconductor junction so as to produce a preprocessed signal including a resistance error term; and a temperature to voltage converter stage for converting the preprocessed signal to a voltage proportional to absolute temperature representing the absolute temperature of the semiconductor junction; wherein the system is configured and arranged so as to remove the resistance error term so as to produce a resistance error free signal representative of the semiconductor junction temperature.