Patents by Inventor Gerhard Hellner
Gerhard Hellner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240121934Abstract: A processor may form a first power line and a second power line. The processor may form a first memory cell with at least six transistors and a second memory cell with at least six transistors. The first pair of transistors of the first memory cell may be stacked vertically and connected at a common net. The common net may be arranged transverse to the first pair of transistors. The first pair of transistors may be configured to share the first power line. The second pair of transistors of the first memory cell may be stacked vertically and connected at a common net. The common net may be arranged transverse to the second pair of transistors. The second pair of transistors may be configured to share the second power line. The transistors of the first pair of transistors are configured to operate independently from the second pair of transistors.Type: ApplicationFiled: December 22, 2022Publication date: April 11, 2024Inventors: Jens Künzer, Tobias Werner, Iris Maria Leefken, Gerhard Hellner
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Patent number: 9904754Abstract: Generating layouts of nets connecting connection terminals of cells in an integrated circuit. Cell layouts of the cells with parameterized locations of the connection terminals, a connection specification of nets specifying electrical connections between the connection terminals, and design rules for the laying out of the nets, are received. A placed layout is generated with the cell layouts placed adjacent to each other in a row. The cell layouts are placed in the row enabling minimization of a selected function. According to the design rules, the nets are laid out as straight interconnects being parallel to a reference straight line using the parameterized locations of the connection terminals in the cell layouts. The laying out includes varying locations of the parameterized locations of the interconnection terminals.Type: GrantFiled: June 29, 2016Date of Patent: February 27, 2018Assignee: International Business Machines CorporationInventors: Gerhard Hellner, Iris M. Leefken, Silke Penth, Tobias Werner
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Patent number: 9898571Abstract: Generating layouts of nets connecting connection terminals of cells in an integrated circuit. Cell layouts of the cells with parameterized locations of the connection terminals, a connection specification of nets specifying electrical connections between the connection terminals, and design rules for the laying out of the nets, are received. A placed layout is generated with the cell layouts placed adjacent to each other in a row. The cell layouts are placed in the row enabling minimization of a selected function. According to the design rules, the nets are laid out as straight interconnects being parallel to a reference straight line using the parameterized locations of the connection terminals in the cell layouts. The laying out includes varying locations of the parameterized locations of the interconnection terminals.Type: GrantFiled: February 5, 2016Date of Patent: February 20, 2018Assignee: International Business Machines CorporationInventors: Gerhard Hellner, Iris M. Leefken, Silke Penth, Tobias Werner
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Patent number: 9767872Abstract: An electronic circuit is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal.Type: GrantFiled: July 28, 2016Date of Patent: September 19, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Gerhard Hellner, Michael Kugel, Rolf Sautter
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Publication number: 20170228487Abstract: Generating layouts of nets connecting connection terminals of cells in an integrated circuit. Cell layouts of the cells with parameterized locations of the connection terminals, a connection specification of nets specifying electrical connections between the connection terminals, and design rules for the laying out of the nets, are received. A placed layout is generated with the cell layouts placed adjacent to each other in a row. The cell layouts are placed in the row enabling minimization of a selected function. According to the design rules, the nets are laid out as straight interconnects being parallel to a reference straight line using the parameterized locations of the connection terminals in the cell layouts. The laying out includes varying locations of the parameterized locations of the interconnection terminals.Type: ApplicationFiled: June 29, 2016Publication date: August 10, 2017Inventors: Gerhard Hellner, Iris M. Leefken, Silke Penth, Tobias Werner
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Publication number: 20170228489Abstract: Generating layouts of nets connecting connection terminals of cells in an integrated circuit. Cell layouts of the cells with parameterized locations of the connection terminals, a connection specification of nets specifying electrical connections between the connection terminals, and design rules for the laying out of the nets, are received. A placed layout is generated with the cell layouts placed adjacent to each other in a row. The cell layouts are placed in the row enabling minimization of a selected function. According to the design rules, the nets are laid out as straight interconnects being parallel to a reference straight line using the parameterized locations of the connection terminals in the cell layouts. The laying out includes varying locations of the parameterized locations of the interconnection terminals.Type: ApplicationFiled: February 5, 2016Publication date: August 10, 2017Inventors: Gerhard Hellner, Iris M. Leefken, Silke Penth, Tobias Werner
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Patent number: 9564188Abstract: An electronic circuit comprising is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal.Type: GrantFiled: August 31, 2015Date of Patent: February 7, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Gerhard Hellner, Michael Kugel, Rolf Sautter
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Publication number: 20160336049Abstract: An electronic circuit is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal.Type: ApplicationFiled: July 28, 2016Publication date: November 17, 2016Applicant: International Business Machines CorporationInventors: Alexander Fritsch, Gerhard Hellner, Michael Kugel, Rolf Sautter
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Patent number: 9484073Abstract: The invention relates to a current sense amplifier. The current sense amplifier comprises: a first NAND gate comprising an output terminal being connected to a first output terminal, a second NAND gate comprising an output terminal being connected to a second output terminal, a first cross coupled inverter, and a second cross coupled inverter, the first inverter comprising a first n-FET and the second inverter comprising a second n-FET, a transmission gate comprising a first and a second transmission terminal and a transmission control terminal, the transmission control terminal being connected to a sense control line input terminal, a third n-FET having a source connected to a sense current input terminal and a drain connected to a source of the first n-FET, a fourth n-FET having a source connected to a reference current input terminal and a drain connected to a source of the second n-FET.Type: GrantFiled: December 15, 2015Date of Patent: November 1, 2016Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Gerhard Hellner, Iris M. Leefken, Rolf Sautter
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Publication number: 20160071555Abstract: An electronic circuit comprising is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal.Type: ApplicationFiled: August 31, 2015Publication date: March 10, 2016Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Fritsch, Gerhard Hellner, Michael Kugel, Rolf Sautter
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Publication number: 20080016437Abstract: A computer-implemented method and program product of modifying and presenting document data (150). Sub-elements (180) of document elements (TA) are marked as “fixed” elements. When the document data is presented in a visible document area of a computer program processing the document, the fixed elements are presented as long as their associated document elements are presented at least partially. An example for a document element is a table (TA), and its sub-elements can be table headers (180), table rows, and table columns. The associated data used for the presentation are called sliding table headers (430), sliding rows, and sliding columns.Type: ApplicationFiled: March 22, 2007Publication date: January 17, 2008Inventors: Joachim Fenkes, Gerhard Hellner, Tobias Warner, Pascal Witte
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Patent number: 6496398Abstract: The present invention relates to content addressable memory (CAM), particularly, to a CAM having its memory array, which contains a plurality of memory locations, being divided into at least a first and a second memory block (100, 102), whereby the first and second memory block (100, 102) are formed by a first and second portion of each of said memory locations, respectively. The CAM further comprises a first set of compare lines (115) and a first set-of match lines (116) associated to said first memory block (100), and a second set of compare lines (117) and a second set of match lines (118) associated to said second memory block (102), and pre-charge units (112, 114) for charging said match lines before a comparison operation. The present invention provides an improved CAM which allows flagging of memory locations of which the content only partially matches a given comparison value.Type: GrantFiled: December 6, 2001Date of Patent: December 17, 2002Assignee: International Business Machines CorporationInventors: Gerhard Hellner, Rolf Sautter, Otto Martin Wagner
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Publication number: 20020075713Abstract: The present invention relates to content addressable memory (CAM), particularly, to a CAM having its memory array, which contains a plurality of memory locations, being divided into at least a first and a second memory block (100, 102), whereby the first and second memory block (100, 102) are formed by a first and second portion of each of said memory locations, respectively. The CAM further comprises a first set of compare lines (115) and a first set of match lines (116) associated to said first memory block (100), and a second set of compare lines (117) and a second set of match lines (118) associated to said second memory block (102), and pre-charge units (112, 114) for charging said match lines before a comparison operation. The present invention provides an improved CAM which allows flagging of memory locations of which the content only partially matches a given comparison value.Type: ApplicationFiled: December 6, 2001Publication date: June 20, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerhard Hellner, Rolf Sautter, Otto Martin Wagner