Patents by Inventor Gernot E. Guenther
Gernot E. Guenther has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7945433Abstract: A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs.Type: GrantFiled: April 30, 2007Date of Patent: May 17, 2011Assignee: International Business Machines CorporationInventors: Daniel R. Crouse, II, Gernot E. Guenther, Viktor Gyuris, Harrell Hoffman, Kevin A. Pasnik, Thomas J. Tryt, John H. Westermann, Jr.
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Patent number: 7865346Abstract: A hardware simulation accelerator to simulate logic designs, a method to encode instructions for use in the hardware simulation accelerator, and a computer program product having code of the method by which the hardware simulation accelerator can read encoded instructions to simulate the logic design, and computer program product of the encoded instructions to simulate a logic design in a hardware accelerator. Each instruction has one of a plurality of opcodes, the opcodes select which of the hardware resources of the hardware simulation accelerator will implement and use the values set forth in other programmable bits of the encoded instruction. The encoded instruction may be a routing and/or a gate evaluation instruction.Type: GrantFiled: March 30, 2007Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Gernot E. Günther, Viktor Gyuris, Kevin Anthony Pasnik, Thomas John Tryt, John H. Westermann, Jr.
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Patent number: 7769577Abstract: A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.Type: GrantFiled: August 31, 2007Date of Patent: August 3, 2010Assignee: International Business Machines CorporationInventors: Gernot E. Guenther, Viktor Gyuris, Harrell Hoffman, Kevin Anthony Pasnik, John Henry Westerman, Jr.
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Patent number: 7562320Abstract: An ASIC based hardware accelerated simulation engine accelerates logic verification of integrated circuit designs utilizing a field of ASIC chips interconnected by direct connections. Communication between the chips has to be accomplished by switching technology internal to the chips. The switching technology employing programmable cross-point switches; i.e. hardware elements with input, output and command ports which propagate signals from the input ports to the output ports following a given permutation determined by values on the command port. The ASIC chip contains an instruction memory to program the logic elements thereof. A conveyor belt based implementation of the programmable cross-point switches provides reduced command bit requirements.Type: GrantFiled: September 15, 2006Date of Patent: July 14, 2009Assignee: International Business Machines CorporationInventors: Gernot E. Guenther, Viktor Sandor Gyuris, Thomas J. Tryt, John H. Westerman, Jr.
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Publication number: 20080270748Abstract: A system and method for design verification and, more particularly, a hardware simulation accelerator design and method that exploits a parallel structure of user models to support a large user model size. The method includes a computer including N number of logic evaluation units (LEUs) that share a common pool of instruction memory (IM). The computer infrastructure is operable to: partition a number of parallel operations in a netlist; and send a same instruction stream of the partitioned number of parallel operations to N number of LEUs from a single IM. The system is a hardware simulation accelerator having a computer infrastructure operable to provide a stream of instructions to multiple LEUs from a single IM. The multiple LEUs are clustered together with multiple IMs such that each LEU is configured to use instructions from any of the multiple IMs thereby allowing a same instruction stream to drive the multiple LEUs.Type: ApplicationFiled: April 30, 2007Publication date: October 30, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel R. CROUSE, Gernot E. GUENTHER, Viktor GYURIS, Harrell HOFFMAN, Kevin A. PASNIK, Thomas J. TRYT, John H. WESTERMANN
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Publication number: 20080243462Abstract: A hardware simulation accelerator to simulate logic designs, a method to encode instructions for use in the hardware simulation accelerator, and a computer program product having code of the method by which the hardware simulation accelerator can read encoded instructions to simulate the logic design, and computer program product of the encoded instructions to simulate a logic design in a hardware accelerator. Each instruction has one of a plurality of opcodes, the opcodes select which of the hardware resources of the hardware simulation accelerator will implement and use the values set forth in other programmable bits of the encoded instruction. The encoded instruction may be a routing and/or a gate evaluation instruction.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: International Business Machines CorporationInventors: Gernot E. Guenther, Viktor Gyuris, Kevin Anthony Pasnik, Thomas John Tryt, John H. Westermann
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Publication number: 20080127006Abstract: Method, system, and program product for expanding the effective capacity of embedded memory by storing data in a compressed form and reading the data out with subsequent data decompression, including adaptive decompression and data conversion. The system and method for compression and decompression of HDL code between HDL code storage and HDL code processing for simulation of a device or system.Type: ApplicationFiled: October 27, 2006Publication date: May 29, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gernot E. Guenther, Viktor S. Gyuris, Thomas J. Tryt, John H. Westermann
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Publication number: 20080127012Abstract: An ASIC based hardware accelerated simulation engine accelerates the process of logic verification of integrated circuit designs utilizing a field of ASIC chips. The ASIC chips are interconnected by direct connections, with the communication between these chips has to be accomplished by switching technology internal to the chips. The switching technology employs programmable cross-points, that is, hardware elements with input, output and command ports. The programmable cross-points propagate signals from their input ports to their output ports following a given permutation determined by the values on the command port. To program the various logic elements of ASIC chip, the ASIC chip contains an instruction memory. This invention provides a conveyor belt based implementation of the programmable cross-point that has reduced command bit requirements compared to the prior art solution.Type: ApplicationFiled: September 15, 2006Publication date: May 29, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gernot E. Guenther, Viktor Sandor Gyuris, Thomas J. Tryt, John H. Westerman
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Patent number: 7290228Abstract: A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.Type: GrantFiled: February 24, 2005Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Gernot E. Guenther, Viktor Gyuris, Harrell Hoffman, Kevin Anthony Pasnik, John Henry Westermann, Jr.