Abstract: A display device for measuring the end-to-end latency of a computing system. The computing system includes an input device, a computing device, and the display device. The display device is directly connected with the input device and receives input data packets generated by the input device in response to received user input events. The display device passes the input packets to the computing device for graphics processing. The display device measures the end-to-end latency comprising the sum of three latencies. A first latency comprises an input delay of the input device. A second latency comprises an amount of time between generation of the input packet and a corresponding change in pixel values caused by the input event at the display device. A third latency comprises a display latency. The display device also displays latency information associated with the measured end-to-end latency.

Abstract: In various examples, a low-latency variable backlight liquid crystal display (LCD) system is disclosed. The LCD system may reduce latency and video lag by performing an analysis of peak pixel values within subsets of pixels using a rendering device, prior to transmitting the frame to a display device for display. As a result, the display device may receive the peak pixel value data prior to or concurrently with the frame data, and may begin updating the backlight settings of the display without having to wait for a substantial portion of the frame to be received. In this way, the LCD system may avoid the full frame delay of conventional systems, allowing the LCD system to more reliably support high-performance applications such as gaming.

Abstract: In various examples, a low-latency variable backlight liquid crystal display (LCD) system is disclosed. The LCD system may reduce latency and video lag by performing an analysis of peak pixel values within subsets of pixels using a rendering device, prior to transmitting the frame to a display device for display. As a result, the display device may receive the peak pixel value data prior to or concurrently with the frame data, and may begin updating the backlight settings of the display without having to wait for a substantial portion of the frame to be received. In this way, the LCD system may avoid the full frame delay of conventional systems, allowing the LCD system to more reliably support high-performance applications such as gaming.

Abstract: A display device for measuring the end-to-end latency of a computing system. The computing system includes an input device, a computing device, and the display device. The display device is directly connected with the input device and receives input data packets generated by the input device in response to received user input events. The display device passes the input packets to the computing device for graphics processing. The display device measures the end-to-end latency comprising the sum of three latencies. A first latency comprises an input delay of the input device. A second latency comprises an amount of time between generation of the input packet and a corresponding change in pixel values caused by the input event at the display device. A third latency comprises a display latency. The display device also displays latency information associated with the measured end-to-end latency.

Abstract: A display controller progressively updates LEDs and LCD pixels in scanline order as portions of an image are scanned into a frame buffer. The display controller analyzes a first portion of the image that includes a first pixel value associated with a first LCD pixel. The display controller identifies a first LED that contributes luminance to the first LCD pixel and determines an LED current setting for the LED based on the first pixel value. The display controller then identifies a second LCD pixel that resides above the first LED and is associated with a second pixel value. The display controller configures the second LCD pixel based on the second pixel value and luminance contributions received at the second LCD pixel. Accordingly, the display controller need not wait for the entire image to be scanned into the frame buffer before initiating display of the image.

Abstract: A display controller progressively updates LEDs and LCD pixels in scanline order as portions of an image are scanned into a frame buffer. The display controller analyzes a first portion of the image that includes a first pixel value associated with a first LCD pixel. The display controller identifies a first LED that contributes luminance to the first LCD pixel and determines an LED current setting for the LED based on the first pixel value. The display controller then identifies a second LCD pixel that resides above the first LED and is associated with a second pixel value. The display controller configures the second LCD pixel based on the second pixel value and luminance contributions received at the second LCD pixel. Accordingly, the display controller need not wait for the entire image to be scanned into the frame buffer before initiating display of the image.

Abstract: One embodiment of the present invention sets forth a technique for reducing motion blur in a liquid crystal display (LCD) by pulsing each frame with a relatively short pulse of backlight illumination while driving pixels within the LCD with compensated intensity values to account for LCD settling time and vertical position. An LCD drive compensation unit implements the disclosed technique to generate an intensity value for each pixel that is scanned into the LCD. The technique advantageously reduces motion blur while preserving uniform vertical display accuracy.

Abstract: One embodiment of the present invention sets forth a technique for reducing motion blur in a liquid crystal display (LCD) by pulsing each frame with a relatively short pulse of backlight illumination while driving pixels within the LCD with compensated intensity values to account for LCD settling time and vertical position. An LCD drive compensation unit implements the disclosed technique to generate an intensity value for each pixel that is scanned into the LCD. The technique advantageously reduces motion blur while preserving uniform vertical display accuracy.

Abstract: A method includes reducing a red rivalry through adjusting a color temperature on a first image, converting the first image from the RGB domain to a YCbCr domain, shifting a hue of a red color in the first image towards a magenta color to reduce a red color vibrancy, and adjusting a blue color in the first image such that a dark blue visible through a second lens corresponding to a second image is at least partially visible through a first lens corresponding to the first image. The method also includes reducing the red rivalry through adjusting a tone of the red color in the first image towards a brown color, converting the first image from the YCbCr domain back to the RGB domain, adjusting a color saturation in the first image, and combining the first image with the second image in a processor to generate an anaglyph image.

Abstract: A method includes reducing a red rivalry through adjusting a color temperature on a first image, converting the first image from the RGB domain to a YCbCr domain, shifting a hue of a red color in the first image towards a magenta color to reduce a red color vibrancy, and adjusting a blue color in the first image such that a dark blue visible through a second lens corresponding to a second image is at least partially visible through a first lens corresponding to the first image. The method also includes reducing the red rivalry through adjusting a tone of the red color in the first image towards a brown color, converting the first image from the YCbCr domain back to the RGB domain, adjusting a color saturation in the first image, and combining the first image with the second image in a processor to generate an anaglyph image.

Abstract: The present invention sets forth a method and system for mating a signal transmitting device and a viewing device. In one embodiment, the method includes determining presence of the signal transmitting device and the viewing device, selecting a unique code from a pre-determined group of codes assigned to the signal transmitting device, and sending the unique code to the viewing device for the viewing device to decipher data packets from the signal transmitting device.

Abstract: A multiport register file includes a first file unit having registers of a first width and a second file unite having registers of a second width. The second width being less than the first width. The first file unit accommodates data destined to be operands for functional units of a VLIW processor, or result data from those functional units. The second file unit accommodates guard bits for conditioning operation of those functional units.

Abstract: Custom operations are useable in processor systems for performing functions including multimedia functions. These custom operations enhance a system, such as PC system, to provide real-time multimedia capabilities while maintaining advantages of a special-purpose, embedded solution, i.e., low cost and chip count, and advantages of a general-purpose processor reprogramability. These custom operations work in a computer system which supplies input data having at least two operand data, performs operations on the operand data, and supplies result data to a destination register.

Abstract: Cost/performance of VLIW architecture is improved by reducing the number of slots in the instruction issue register.

Abstract: Cost/performance of VLIW architecture is improved by reducing the number of slots in the instruction issue register.

Abstract: A VLIW processor has less instruction issue slots than functional units. Operands and results for the operations specified by the instruction issue register are stored in a multiport register file. The multiport register file has numbers of read and write ports which are tied to the number of instruction issue slots rather than to the number of functional units. A write control unit controls transfer of results from functional units to the multiport register file to take into account instruction latency.

Abstract: A circuit for processing a jump operation also enables handling pending interrupts or exceptions. The jump operation has an operand specifying a destination address. If an interrupt or exception is pending, a destination program counter is set to the contents of the operand. Then the program counter is set to an interrupt or exception handler address. If no interrupt or exception is pending, then the program counter is set to the destination address.

Abstract: Custom operations are useable in processor systems for performing functions including multimedia functions. These custom operations enhance a system, such as PC system, to provide real-time multimedia capabilities while maintaining advantages of a special-purpose, embedded solution, i.e., low cost and chip count, and advantages of a general-purpose processor reprogramability. These custom operations work in a computer system which supplies input data having operand data, performs operations on the operand data, and supplies result data to a destination register. Operations performed may include audio and video processing including clipping or saturation operations. The present invention also performs parallel operations on select operand data from input registers and stores results in the destination register.

Abstract: Cost/performance of VLIW architecture is improved by reducing the number of slots in the instruction issue register.

Abstract: A processing device performs operations in response to program instructions. In particular, values are written to a data memory of the system, which alters a defined visible state of the system. In the event of an exception (e.g. a pagefault or TLB miss in a virtual memory system), control returns to a recent checkpoint instruction after handling the exception, and instructions are re-executed. A record/replay circuit is provided in the form of an event memory, which remembers only those values read from the data memory since the last checkpoint. During the re-execution, the recorded values are reproduced instead of performing actual memory reads, and all memory accesses are suppressed. When the re-execution reaches the point where execution was originally interrupted, recording begins again to prepare for any further exception which may arise before the next checkpoint.