Patents by Inventor Gerrit den Besten

Gerrit den Besten has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8497713
    Abstract: A differential switched-current line-driver implements a method to reduce power consumption by eliminating output current that does not contribute to the required differential output signal. This output current is used for example during a training phase, and the current elimination can take place after the training phase is complete.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: July 30, 2013
    Assignee: NXP B.V.
    Inventor: Willem Gerrit den Besten
  • Publication number: 20120119794
    Abstract: A differential switched-current line-driver implements a method to reduce power consumption by eliminating output current that does not contribute to the required differential output signal. This output current is used for example during a training phase, and the current elimination can take place after the training phase is complete.
    Type: Application
    Filed: November 14, 2011
    Publication date: May 17, 2012
    Applicant: NXP B.V.
    Inventor: Willem Gerrit den Besten
  • Patent number: 7236551
    Abstract: There is a clock recovery circuit to correct the timing relationship between a data signal and clock signal. The clock recovery circuit comprises a phase detector having an input for receiving a clock signal having a period, an input for receiving a data signal, and an input for receiving a window signal. The window signal has a period equal to the period of the clock signal and phase difference of ?90° with respect to the clock signal. The phase detector generates an up output and a down output while maintaining a phase relationship of the up output and the down output in response to the phase relationship between the clock signal and the data signal.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: June 26, 2007
    Assignee: NXP B.V.
    Inventors: Geertjan Joordens, Gerrit den Besten
  • Publication number: 20040061539
    Abstract: There is a clock recovery circuit to correct the timing relationship between a data signal and clock signal. The clock recovery circuit comprises a phase detector having an input for receiving a clock signal having a period, an input for receiving a data signal, and an input for receiving a window signal. The window signal has a period equal to the period of the clock signal and phase difference of −90° with respect to the clock signal. The phase detector generates an up output and a down output while maintaining a phase relationship of the up output and the down output in response to the phase relationship between the clock signal and the data signal.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 1, 2004
    Inventors: Geertjan Joordens, Gerrit den Besten