Abstract: A program voltage signal implemented as a series of increasing program voltage pulses is applied to a set of non-volatile storage elements. Different increment values can be used when programming memory cells to different memory states. A smaller increment value can be used when programming memory cells to lower threshold voltage memory states and a larger increment value used when programming memory cells to higher threshold voltage memory states such as the highest memory state in an implementation. When non-volatile storage elements of a set are programmed to different memory states under simultaneous application of a single program voltage signal, programming can be monitored to determine when lower state programming is complete. The increment value can then be increased to complete programming to the highest memory state.

Abstract: A program pulse is applied to a set of non-volatile storage elements. The magnitude of the program pulse is chosen to be low enough such that no non-volatile storage elements will be over programmed. The non-volatile storage elements are tested to determine whether at least one non-volatile storage element (or some other minimum number) has been programmed past a test threshold. If so, the set of non-volatile memory elements is considered to have one or more fast programming non-volatile storage elements and future programming is performed using a smaller increment value for subsequent program pulses. If the set of non-volatile memory elements is not determined to have one or more fast programming non-volatile storage elements, then a larger increment value is used for subsequent program pulses until one non-volatile storage element (or some other minimum number) has been programmed past the test threshold, at which point the smaller increment value is used for subsequent program pulses.

Abstract: Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create lower doped regions of a first conductivity type in the substrate on drain sides of the stacked gate structures. The source implantations create higher doped regions of the first conductivity type in the substrate on source sides of the stacked gate structures.

Abstract: A low voltage of the order of or one to three volts instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a NAND flash device to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes. In a modified erased area self boosting scheme, low voltages are applied to two or more word lines on the source side of the selected word line to reduce band-to-band tunneling and to improve the isolation between two boosted channel regions.