Patents by Inventor Gertjan Hemink
Gertjan Hemink has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7321509Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.Type: GrantFiled: February 16, 2007Date of Patent: January 22, 2008Assignee: Sandisk CorporationInventors: Jian Chen, Raul-Adrian Cernea, Gertjan Hemink
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Publication number: 20070140006Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.Type: ApplicationFiled: February 16, 2007Publication date: June 21, 2007Inventors: Jian Chen, Raul-Adrian Cernea, Gertjan Hemink
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Patent number: 7035146Abstract: One or more programming operations are performed on a set of non-volatile storage elements. For example, the programming operations may include applying a set of programming pulses. A verify process is performed to determine which of the non-volatile storage element have reached an intermediate verify threshold but have not reached a final verify threshold. One additional programming operation at a reduced level is performed for the non-volatile storage elements that have reached the intermediate verify threshold but have not reached the final verify threshold, and those non-volatile storage elements are then inhibited from further programming. Non-volatile storage elements that have not reached the intermediate verify threshold continue programming. Non-volatile storage elements that reach the final verify threshold are inhibited from programming.Type: GrantFiled: March 15, 2005Date of Patent: April 25, 2006Assignee: Sandisk CorporationInventors: Gertjan Hemink, Yupin Fong
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Publication number: 20050157552Abstract: One or more programming operations are performed on a set of non-volatile storage elements. For example, the programming operations may include applying a set of programming pulses. A verify process is performed to determine which of the non-volatile storage element have reached an intermediate verify threshold but have not reached a final verify threshold. One additional programming operation at a reduced level is performed for the non-volatile storage elements that have reached the intermediate verify threshold but have not reached the final verify threshold, and those non-volatile storage elements are then inhibited from further programming. Non-volatile storage elements that have not reached the intermediate verify threshold continue programming. Non-volatile storage elements that reach the final verify threshold are inhibited from programming.Type: ApplicationFiled: March 15, 2005Publication date: July 21, 2005Inventors: Gertjan Hemink, Yupin Fong
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Patent number: 6888758Abstract: One or more programming operations are performed on a set of non-volatile storage elements. For example, the programming operations may include applying a set of programming pulses. A verify process is performed to determine which of the non-volatile storage element have reached an intermediate verify threshold but have not reached a final verify threshold. One additional programming operation at a reduced level is performed for the non-volatile storage elements that have reached the intermediate verify threshold but have not reached the final verify threshold, and those non-volatile storage elements are then inhibited from further programming. Non-volatile storage elements that have not reached the intermediate verify threshold continue programming. Non-volatile storage elements that reach the final verify threshold are inhibited from programming.Type: GrantFiled: January 21, 2004Date of Patent: May 3, 2005Assignee: Sandisk CorporationInventors: Gertjan Hemink, Yupin Fong
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Patent number: 6188611Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.Type: GrantFiled: September 29, 1999Date of Patent: February 13, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuo Endoh, Yoshiyuki Tanaka, Seiichi Aritome, Riichiro Shirota, Susumu Shuto, Tomoharu Tanaka, Gertjan Hemink, Toru Tanzawa
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Patent number: 6014330Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.Type: GrantFiled: October 8, 1998Date of Patent: January 11, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuo Endoh, Yoshiyuki Tanaka, Seiichi Aritome, Riichiro Shirota, Susumu Shuto, Tomoharu Tanaka, Gertjan Hemink, Toru Tanzawa
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Patent number: 5949714Abstract: In a nonvolatile semiconductor memory device including a memory cell array obtained by arranging, in a matrix manner, electrically programmable memory cells, each of which comprises stacking a charge storage layer and a control gate on a semiconductor layer through an insulating film, the threshold voltages of the memory cells are detected after erasing, and data are programmed in a fast programmable cell at a relatively low voltage and in a slow programmable cell at a relatively high voltage, thereby suppressing variations in threshold voltages after programming within the same period of programming time.Type: GrantFiled: November 13, 1998Date of Patent: September 7, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Gertjan Hemink, Tomoharu Tanaka
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Patent number: 5946231Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on the semiconductor substrate, the memory cell being capable of electrically rewriting data by exchanging charges between the charge storage layer and the semiconductor substrate, and a means for applying a high potential to the semiconductor substrate and an intermediate potential to the control gate in a first data erase operation, and applying a high potential to the semiconductor substrate and a low potential to the control gate in second and subsequent data erase operations, thereby removing electrons from the charge storage layer.Type: GrantFiled: May 5, 1998Date of Patent: August 31, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuo Endoh, Yoshiyuki Tanaka, Seiichi Aritome, Riichiro Shirota, Susumu Shuto, Tomoharu Tanaka, Gertjan Hemink, Toru Tanzawa
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Patent number: 5870334Abstract: In a nonvolatile semiconductor memory device including a memory cell array obtained by arranging, in a matrix manner, electrically programmable memory cells, each of which comprises stacking a charge storage layer and a control gate on a semiconductor layer through an insulating film, the threshold voltages of the memory cells are detected after erasing, and data are programmed in a fast programmable cell at a relatively low voltage and in a slow programmable cell at a relatively high voltage, thereby suppressing variations in threshold voltages after programming within the same period of programming time.Type: GrantFiled: June 11, 1997Date of Patent: February 9, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Gertjan Hemink, Tomoharu Tanaka
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Patent number: RE41019Abstract: An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation.Type: GrantFiled: June 13, 2006Date of Patent: December 1, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Gertjan Hemink
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Patent number: RE41020Abstract: An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation.Type: GrantFiled: June 13, 2006Date of Patent: December 1, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Gertjan Hemink
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Patent number: RE41021Abstract: An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation.Type: GrantFiled: June 13, 2006Date of Patent: December 1, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Gertjan Hemink
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Patent number: RE41244Abstract: An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation.Type: GrantFiled: June 13, 2006Date of Patent: April 20, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Gertjan Hemink
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Patent number: RE41456Abstract: An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation.Type: GrantFiled: June 13, 2006Date of Patent: July 27, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Gertjan Hemink
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Patent number: RE41468Abstract: An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis on the contents of the data circuits and the states of the memory cells set upon the write operation.Type: GrantFiled: June 13, 2006Date of Patent: August 3, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Gertjan Hemink
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Patent number: RE41485Abstract: An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation.Type: GrantFiled: June 13, 2006Date of Patent: August 10, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Gertjan Hemink
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Patent number: RE41950Abstract: An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation.Type: GrantFiled: June 13, 2006Date of Patent: November 23, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Gertjan Hemink
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Patent number: RE41969Abstract: An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation.Type: GrantFiled: June 13, 2006Date of Patent: November 30, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Gertjan Hemink
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Patent number: RE42120Abstract: An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation.Type: GrantFiled: June 13, 2006Date of Patent: February 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Gertjan Hemink