Abstract: Disclosed are an anode including a core part and a binder and a secondary battery including the same. Particularly, a coating layer including a polymer is provided between the core part and the binder and thus blocks electron transport paths from the core part to the binder. Thereby, decomposition of the binder is suppressed, and thus, the charge capacity and the initial Coulombic efficiency of the secondary battery are increased.

Abstract: The present invention relates to a method of recycling C-14 in a spent resin, the method includes: i) heating a spent resin raw material including 14CO2 in the presence of moisture by microwave irradiation; ii) refluxing, by condensation, water vapor in a first processing gas produced by the microwave irradiation and released from the spent resin raw material; and iii) removing water vapor from the first processing gas by the refluxing, and transporting a second processing gas including 14CO2, which is released from the spent resin raw material, to the outside, and to an apparatus for recycling the same.

Abstract: A clock distribution circuit may include a data clock generation circuit configured to be input a power source voltage and configured to generate an internal clock signal according to an external clock signal; and a global distribution circuit includes a first circuit and a second circuit coupled to a global line, configured to be input a power source voltage and configured to receive the internal clock signal through the first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through the second circuit, wherein a first bias voltage provided to the first circuit and a second bias voltage provided to the second circuit are controlled independently of each other.

Abstract: A system may include an external apparatus and a semiconductor apparatus. The semiconductor apparatus may be configured to communicate with the external apparatus by receiving a frequency-varying first clock signal provided from the external apparatus.

Abstract: A semiconductor apparatus includes: a pad unit comprising a plurality of data input/output (I/O) pads and a plurality of error detection code pads; an error detection code (EDC) read path configured to generate a plurality of EDCs by performing an error detection operation on a plurality of data, and output the plurality of EDCs through the plurality of error detection code pads; a comparison circuit configured to generate a comparison result signal by comparing the plurality of EDCs; and a data read path configured to output the comparison result signal through any one of the plurality of data I/O pads.

Abstract: A clock distribution circuit may include a data clock generation circuit configured to be input a power source voltage and configured to generate an internal clock signal according to an external clock signal; and a global distribution circuit includes a first circuit and a second circuit coupled to a global line, configured to be input a power source voltage and configured to receive the internal clock signal through the first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through the second circuit, wherein a first bias voltage provided to the first circuit and a second bias voltage provided to the second circuit are controlled independently of each other.

Abstract: A semiconductor memory device may include a control signal generation circuit, a period signal generation circuit and a selection circuit. The control signal generation circuit may be configured to generate a control signal in response to a mode signal, a voltage detection signal and a temperature detection signal. The period signal generation circuit may be configured to generate a period signal periodically transited in response to the control signal. The selection circuit may be configured to output, in response to the control signal, any one of the period signal and a signal from an external device that is buffered.

Abstract: A system may include an external apparatus and a semiconductor apparatus. The semiconductor apparatus may be configured to communicate with the external apparatus by receiving a frequency-varying first clock signal provided from the external apparatus.

Abstract: A semiconductor apparatus includes: a pad unit comprising a plurality of data input/output (I/O) pads and a plurality of error detection code pads; an error detection code (EDC) read path configured to generate a plurality of EDCs by performing an error detection operation on a plurality of data, and output the plurality of EDCs through the plurality of error detection code pads; a comparison circuit configured to generate a comparison result signal by comparing the plurality of EDCs; and a data read path configured to output the comparison result signal through any one of the plurality of data I/O pads.

Abstract: A semiconductor memory device may include a control signal generation circuit, a period signal generation circuit and a selection circuit. The control signal generation circuit may be configured to generate a control signal in response to a mode signal, a voltage detection signal and a temperature detection signal. The period signal generation circuit may be configured to generate a period signal periodically transited in response to the control signal. The selection circuit may be configured to output, in response to the control signal, any one of the period signal and a signal from an external device that is buffered.

Abstract: A clock distribution circuit may include a data clock generation circuit configured to generate an internal clock signal using an external clock signal. The clock distribution circuit may be configured to receive the internal clock signal through a first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through a second circuit coupled to a global line. A first bias voltage provided to the first circuit and the data clock generation circuit and a second bias voltage provided to the second circuit may be controlled independently of each other.

Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a plurality of memory blocks. The semiconductor apparatus may include a peripheral circuit region arranged between the plurality of memory blocks. A plurality of signal input/output (I/O) pads may be arranged in the plurality of memory blocks.

Abstract: A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.

Abstract: A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.

Abstract: A semiconductor apparatus includes a pipe input/output signal generation block configured to generate a plurality of pipe input signals and a plurality of pipe output signals according to a pipe enable signal, and be initialized according to an error detection signal; a pipe latch group including a plurality of pipe latches, each of the plurality of pipe latches being configured to receive and store an input signal according to a corresponding pipe input signal and output a stored signal as an output signal according to a corresponding pipe output signal; and an error detection block configured to generate the error detection signal according to a pipe end signal, the pipe enable signal, the plurality of pipe input signals and the plurality of pipe output signals.

Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a plurality of memory blocks. The semiconductor apparatus may include a peripheral circuit region arranged between the plurality of memory blocks. A plurality of signal input/output (I/O) pads may be arranged in the plurality of memory blocks.

Abstract: A semiconductor memory device includes a first address input block which receives first information applied from an exterior as a corresponding normal address in a normal mode and receives the first information as a test clock in a test mode, a second address input block which receives second information applied from an exterior as the corresponding normal address in the normal mode and receives the second information as a test code in the test mode, and a test signal generation block which synchronizes the test code with the test clock in the test mode and generates a test command, a test address and a test data in response to a synchronized test code.

Abstract: A semiconductor system may include a first semiconductor configured to output a command signal and an address signal. The semiconductor system may include a second semiconductor device configured to include a first operation circuit including a first MOS transistor and a second operation circuit including a second MOS transistor. The first MOS transistor and the second MOS transistor may be turned on in response to a first internal command signal when a first operation is executed according to the command signal. The first MOS transistor may be turned on in response to a period signal generated from the address signal when a second operation is executed according to the command signal.

Abstract: A semiconductor system is provided, which includes a controller configured to output an active command and test mode signals; and a semiconductor device configured to sense and amplify a pair of bit lines by generating a first power control signal of which a pulse width is adjusted in accordance with a combination of the test mode signals during an enable period of an enable signal generated by the active command, receiving a supply of a first power according to the first power control signal, and receiving a supply of a second power according to a second power control signal.

Abstract: A semiconductor apparatus includes a pipe input/output signal generation block configured to generate a plurality of pipe input signals and a plurality of pipe output signals according to a pipe enable signal, and be initialized according to an error detection signal; a pipe latch group including a plurality of pipe latches, each of the plurality of pipe latches being configured to receive and store an input signal according to a corresponding pipe input signal and output a stored signal as an output signal according to a corresponding pipe output signal; and an error detection block configured to generate the error detection signal according to a pipe end signal, the pipe enable signal, the plurality of pipe input signals and the plurality of pipe output signals.