Patents by Inventor Geunyeong YU
Geunyeong YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128985Abstract: A decoding device and a decoding method which relate to: receiving a codeword; estimating a number of errors included in the received codeword; and decoding the codeword based on the estimated number of errors using at least one of a first parity check matrix and a second parity check matrix, wherein the first parity check matrix corresponds to a first low-density parity check (LDPC) code, and the second parity check matrix corresponds to a second LDPC code, and wherein the first parity check matrix is based on a first code type, and the second parity check matrix is based on a second code type different from the first code type.Type: ApplicationFiled: September 6, 2023Publication date: April 18, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Bohwan Jun, Daeyeol Yang, Hongrak Son, Geunyeong Yu, Youngjun Hwang
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Publication number: 20240120945Abstract: A generalized low-density parity-check (G-LDPC) encoder, including a plurality of generalized constraint (GC) encoders configured to perform a plurality of GC encoding operations in parallel based on a GC code having a quasi-cyclic (QC) structure including information variable nodes, inner parity variable nodes, and super check nodes configured to perform multiple condition checks, wherein each GC encoder of the plurality of GC encoders includes a plurality of first logic circuits configured to perform a GC encoding operation of the plurality of GC encoding operations; and an LDPC encoder configured to perform an LDPC encoding operation based on an LDPC code having the QC structure, wherein the LDPC encoder includes a plurality of single check nodes configured to perform a single parity check, wherein the each GC encoder is configured to receive information bits, and to determine parity bits of a portion of inner parity bits corresponding to the information bits by enabling only a portion of the plurality ofType: ApplicationFiled: July 24, 2023Publication date: April 11, 2024Applicant: SAMSUNG ELECTRONICS CO, LTD.Inventors: Daeyeol YANG, Bohwan JUN, Hongrak SON, Geunyeong YU, Youngjun HWANG
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Publication number: 20240106462Abstract: a G-LDPC decoder is provided. The G-LDPC decoder includes: a generalized check node decoder configured to, in each of a plurality of iterations: group connected variable nodes into groups, the connected variable nodes being connected to an mth generalized check node among generalized check nodes; generate test patterns in each of one or more of the groups based on a first message received by the mth generalized check node from the connected variable nodes; and identify a value of a second message to be provided from the mth generalized check node to the connected variable nodes based on the test patterns; and a LDPC decoder circuitry configured to, in each of the iterations, update a value of an nth variable node, among the variable nodes, based on the second message received by the nth variable node from a generalized check node that is connected to the nth variable node.Type: ApplicationFiled: April 28, 2023Publication date: March 28, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Dae-Yeol Yang, BOHWAN JUN, HONG RAK SON, GEUNYEONG YU, YOUNGJUN HWANG
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Patent number: 11929762Abstract: A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.Type: GrantFiled: August 1, 2022Date of Patent: March 12, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kangseok Lee, Geunyeong Yu, Youngjun Hwang, Hongrak Son, Junho Shin, Bohwan Jun, Hyunseung Han
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Publication number: 20230187011Abstract: In a method of error correction code (ECC) decoding, normal read data are read from a nonvolatile memory device based on normal read voltages, and a first ECC decoding is performed with respect to the normal read data. When the first ECC decoding results in failure, flip read data are read from the nonvolatile memory device based on flip read voltages corresponding to a flip range of a threshold voltage. Corrected read data are generated based on the flip read data by inverting error candidate bits included in the flip range among bits of the normal read data, and a second ECC decoding is performed with respect to the corrected read voltage. Error correction capability may be enhanced by retrying ECC decoding based on the corrected read data when ECC decoding based on the normal read data results in failure.Type: ApplicationFiled: June 30, 2022Publication date: June 15, 2023Inventors: KANGSEOK LEE, GEUNYEONG YU, SEONGHYEOG CHOI, HONGRAK SON, YOUNGJUN HWANG
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Patent number: 11664826Abstract: A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.Type: GrantFiled: September 17, 2021Date of Patent: May 30, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kangseok Lee, Geunyeong Yu, Heeyoul Kwak, Hongrak Son, Dongmin Shin, Wijik Lee, Bohwan Jun, Youngjun Hwang
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Publication number: 20230065578Abstract: Various example embodiments of the inventive concepts provide an error correction circuit and a semiconductor device. The error correction circuit includes clock-sync distributor circuitry configured to output a plurality of distributor output data based on distributor reception data received using a first clock signal, each of the plurality of distributor output data output based on the first clock signal or a second clock signal, the second clock signal having a higher frequency than a frequency of the first clock signal, a node processor configured to generate a plurality of output data by performing error correction decoding using the plurality of distributor output data, output a first subset of the plurality of output data based on the first clock signal, and output a second subset of the plurality of output data based on the second clock signal, and clock-sync combiner circuitry configured to output, based on the first clock signal, the plurality of output data received from the node processor.Type: ApplicationFiled: June 23, 2022Publication date: March 2, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Youngjun HWANG, Hongrak SON, Geunyeong YU
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Patent number: 11562803Abstract: A memory device includes a cell array including a plurality of pages and a control logic configured to control program and read operations of the cell array. The control logic controls the program and read operations to store first through N-th codewords in a first page among the pages and program a page parity corresponding in common to the first through N-th codewords to the first page in response to a program command for a page unit and to selectively read the first codeword among the first through N-th codewords in response to a read command for a sub-page unit, where N is an integer of at least 2. The first codeword includes first sub-page data and a first sub-parity corresponding thereto, and the first sub-parity includes information for correcting an error in the first sub-page data through error correction code (ECC) decoding independently performed on each codeword.Type: GrantFiled: April 29, 2021Date of Patent: January 24, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Youngjun Hwang, Heeyoul Kwak, Bohwan Jun, Hongrak Son, Dongmin Shin, Geunyeong Yu
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Patent number: 11531871Abstract: A stacked neuromorphic device includes a logic die including a control circuit and configured to communicate with a host, and core dies stacked on the logic die and connected to the logic die via through silicon vias (TSVs) extending through the core dies. The core dies include a neuromorphic core die including a synapse array connected to row lines and column lines. The synapse array includes synapses configured to store weights and perform a calculation based on the weights and input data. The weights are included in layers of a neural network system. And the control circuit provides the weights to the neuromorphic core die through the TSVs and controls data transmission by the neuromorphic core die.Type: GrantFiled: April 22, 2020Date of Patent: December 20, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jaehun Jang, Hongrak Son, Changkyu Seol, Geunyeong Yu, Chanho Yoon, Pilsang Yoon
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Patent number: 11531588Abstract: An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.Type: GrantFiled: September 21, 2021Date of Patent: December 20, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Kangseok Lee, Dong-min Shin, Geunyeong Yu, Bohwan Jun, Hee Youl Kwak, Hong Rak Son
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Patent number: 11362868Abstract: A neuromorphic device includes a neuron block, a spike transmission circuit and a spike reception circuit. The neuron block includes a plurality of neurons connected by a plurality of synapses to perform generation and operation of spikes. The spike transmission circuit generates a non-binary transmission signal based on a plurality of transmission spike signals output from the neuron block and transmits the non-binary transmission signal to a transfer channel, where the non-binary transmission signal includes information on transmission spikes included in the plurality of transmission spike signals. The spike reception circuit receives a non-binary reception signal from the transfer channel and generates a plurality of reception spike signals including reception spikes based on the non-binary reception signal to provide the plurality of reception spike signals to the neuron block, where the non-binary reception signal includes information on the reception spikes.Type: GrantFiled: June 25, 2020Date of Patent: June 14, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Changkyu Seol, Hongrak Son, Geunyeong Yu, Pilsang Yoon, Jaehun Jang
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Publication number: 20220182073Abstract: A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.Type: ApplicationFiled: September 17, 2021Publication date: June 9, 2022Inventors: KANGSEOK LEE, Geunyeong Yu, Heeyoul Kwak, Hongrak Son, Dongmin Shin, Wijik Lee, Bohwan Jun, Youngjun Hwang
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Publication number: 20220130485Abstract: A memory device includes a cell array including a plurality of pages and a control logic configured to control program and read operations of the cell array. The control logic controls the program and read operations to store first through N-th codewords in a first page among the pages and program a page parity corresponding in common to the first through N-th codewords to the first page in response to a program command for a page unit and to selectively read the first codeword among the first through N-th codewords in response to a read command for a sub-page unit, where N is an integer of at least 2. The first codeword includes first sub-page data and a first sub-parity corresponding thereto, and the first sub-parity includes information for correcting an error in the first sub-page data through error correction code (ECC) decoding independently performed on each codeword.Type: ApplicationFiled: April 29, 2021Publication date: April 28, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Youngjun HWANG, Heeyoul KWAK, Bohwan JUN, Hongrak SON, Dongmin SHIN, Geunyeong YU
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Publication number: 20220004458Abstract: An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.Type: ApplicationFiled: September 21, 2021Publication date: January 6, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Kangseok LEE, Dong-min SHIN, Geunyeong YU, Bohwan JUN, Hee Youl KWAK, Hong Rak SON
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Patent number: 11184030Abstract: An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.Type: GrantFiled: June 30, 2020Date of Patent: November 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heeyoul Kwak, Jae Hun Jang, Hong Rak Son, Dong-Min Shin, Geunyeong Yu, Kangseok Lee, Hyunseung Han
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Patent number: 11175985Abstract: An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.Type: GrantFiled: June 29, 2020Date of Patent: November 16, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Kangseok Lee, Dong-min Shin, Geunyeong Yu, Bohwan Jun, Hee Youl Kwak, Hong Rak Son
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Publication number: 20210184699Abstract: An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.Type: ApplicationFiled: June 30, 2020Publication date: June 17, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heeyoul Kwak, Jae Hun Jang, Hong Rak Son, Dong-Min Shin, Geunyeong Yu, Kangseok Lee, Hyunseung Han
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Publication number: 20210160109Abstract: A neuromorphic device includes a neuron block, a spike transmission circuit and a spike reception circuit. The neuron block includes a plurality of neurons connected by a plurality of synapses to perform generation and operation of spikes. The spike transmission circuit generates a non-binary transmission signal based on a plurality of transmission spike signals output from the neuron block and transmits the non-binary transmission signal to a transfer channel, where the non-binary transmission signal includes information on transmission spikes included in the plurality of transmission spike signals. The spike reception circuit receives a non-binary reception signal from the transfer channel and generates a plurality of reception spike signals including reception spikes based on the non-binary reception signal to provide the plurality of reception spike signals to the neuron block, where the non-binary reception signal includes information on the reception spikes.Type: ApplicationFiled: June 25, 2020Publication date: May 27, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Changkyu SEOL, Hongrak SON, Geunyeong YU, Pilsang YOON, Jaehun JANG
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Publication number: 20210125045Abstract: A stacked neuromorphic device includes a logic die including a control circuit and configured to communicate with a host, and core dies stacked on the logic die and connected to the logic die via through silicon vias (TSVs) extending through the core dies. The core dies include a neuromorphic core die including a synapse array connected to row lines and column lines. The synapse array includes synapses configured to store weights and perform a calculation based on the weights and input data. The weights are included in layers of a neural network system. And the control circuit provides the weights to the neuromorphic core die through the TSVs and controls data transmission by the neuromorphic core die.Type: ApplicationFiled: April 22, 2020Publication date: April 29, 2021Inventors: JAEHUN JANG, HONGRAK SON, CHANGYU SEOL, GEUNYEONG YU, CHANHO YOON, PILSANG YOON
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Patent number: 10789127Abstract: A method of operating a memory controller that performs decoding by using a parity check matrix corresponding to a convolution-type low density parity check (LDPC) code includes receiving a codeword from at least one memory device, the codeword including a first sub-codeword and a second sub-codeword; decoding a first sub-codeword into first data by using first sliding windows in a first direction, set based on a first sub-matrix included in the parity check matrix and associated with the first sub-codeword; and decoding a second sub-codeword into second data by using second sliding windows in a second direction, set based on a second sub-matrix included in the parity check matrix and associated with the second sub-codeword.Type: GrantFiled: August 8, 2018Date of Patent: September 29, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Geunyeong Yu, Bohwan Jun, Kijun Lee, Junjin Kong, Hong-Rak Son