Patents by Inventor Gi Cheol SHIN

Gi Cheol SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit for physically unclonable function and a method to generate private key for secure authentication using a physically unclonable function cell
    Patent number: 11646899
    Abstract: The present disclosure provides a PUF circuit including a first array including at least one physically unclonable function (PUF) cell, a second array including at least one PUF cell, and a controller which selects a first PUF cell from the first array and selects a second PUF cell from the second array and generates unique information represented by the first PUF cell and the second PUF cell based on a first output voltage output by the first PUF cell and a second output voltage output by the second PUF cell.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: May 9, 2023
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Yoon Myung Lee, Jong Min Lee, Min Sun Kim, Gi Cheol Shin
  • Complementary clock gate and low power flip-flop circuit including same
    Patent number: 11621706
    Abstract: A complementary clock gate, includes a NOR gate configured to receive a data signal D and a signal QI; a first P-type transistor gated by an output value of the NOR gate; and a NAND gate, connected in series to the first P-type transistor, configured to receive a clock signal CK and an inverted data signal DN, and output an inverted clock signal CKB.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: April 4, 2023
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Yoon Myung Lee, Gi Cheol Shin
  • COMPLEMENTARY CLOCK GATE AND LOW POWER FLIP-FLOP CIRCUIT INCLUDING SAME
    Publication number: 20220131533
    Abstract: A complementary clock gate, includes a NOR gate configured to receive a data signal D and a signal QI; a first P-type transistor gated by an output value of the NOR gate; and a NAND gate, connected in series to the first P-type transistor, configured to receive a clock signal CK and an inverted data signal DN, and output an inverted clock signal CKB.
    Type: Application
    Filed: October 8, 2021
    Publication date: April 28, 2022
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Yoon Myung LEE, Gi Cheol SHIN
  • CIRCUIT FOR PHYSICALLY UNCLONABLE FUNCTION AND A METHOD TO GENERATE PRIVATE KEY FOR SECURE AUTHENTICATION USING A PHYSICALLY UNCLONABLE FUNCTION CELL
    Publication number: 20210083886
    Abstract: The present disclosure provides a PUF circuit including a first array including at least one physically unclonable function (PUF) cell, a second array including at least one PUF cell, and a controller which selects a first PUF cell from the first array and selects a second PUF cell from the second array and generates unique information represented by the first PUF cell and the second PUF cell based on a first output voltage output by the first PUF cell and a second output voltage output by the second PUF cell.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 18, 2021
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Yoon Myung LEE, Jong Min LEE, Min Sun KIM, Gi Cheol SHIN