Abstract: Provided are a phase change memory device and a reading method thereof. An example embodiment of a phase change memory device may include main cells programmed to have any one of a plurality of resistance states respectively corresponding to multi-bit data, reference cells programmed to have at least two respectively different resistance states among the resistance states each time the main cells are programmed, and a reference voltage generation circuit sensing the reference cells to generate reference voltages for identifying each of the resistance states.

Abstract: A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.

Abstract: Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.

Abstract: Methods are provided for operating a magnetic random access memory device including a memory cell having a magnetic tunnel junction structure on a substrate. In particular, a writing current pulse may be provided through the magnetic tunnel junction structure, and a writing magnetic field pulse may be provided through the magnetic tunnel junction structure. In addition, at least a portion of the writing magnetic field pulse may be overlapping in time with respect to at least a portion of the writing current pulse, and at least a portion of the writing current pulse and/or at least a portion of the writing magnetic field pulse may be non-overlapping in time with respect to the other. Related devices are also discussed.

Abstract: Methods are provided for operating a magnetic random access memory device including a memory cell having a magnetic tunnel junction structure on a substrate. In particular, a writing current pulse may be provided through the magnetic tunnel junction structure, and a writing magnetic field pulse may be provided through the magnetic tunnel junction structure. In addition, at least a portion of the writing magnetic field pulse may be overlapping in time with respect to at least a portion of the writing current pulse, and at least a portion of the writing current pulse and/or at least a portion of the writing magnetic field pulse may be non-overlapping in time with respect to the other. Related devices are also discussed.

Abstract: Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.

Abstract: A memory device includes a memory cell configured to be coupled to complementary first and second bit lines and a differential amplifier having first and second input terminals and operative to amplify a voltage between the first and second input terminals to produce an output signal. First and second voltage-dependent capacitors are coupled to respective ones of the first and second input terminals, and first and second isolation switches are operative to couple and decouple the first and second bit lines to and from respective ones of the first and second voltage-dependent capacitors. The first and second isolation switches may include respective first and second isolation transistors (e.g., NMOS transistors), and the first and second voltage-dependent capacitors may include respective MOS capacitors.

Abstract: Data sensing circuits for a magnetic memory cell include a current source circuit that selectively supplies a current to the magnetic memory cell. A first storage device selectively coupled to the magnetic memory cell stores a voltage representing a state of the magnetic memory cell. A second storage device selectively coupled to the magnetic memory cell stores a voltage representing a state of the magnetic memory cell. A differential voltage sense circuit coupled to the first and second storage device that is configured to generate a sensed data output signal for the magnetic memory cell responsive to sensing a difference between voltages stored in the first and second storage devices. A control circuit generates control signals to control the current source to supply current to the magnetic memory cell and to control the coupling of the first and second storage devices to the magnetic memory cell. Magnetic memories and methods are also provided.

Abstract: Data sensing circuits for a magnetic memory cell include a current source circuit that selectively supplies a current to the magnetic memory cell. A first storage device selectively coupled to the magnetic memory cell stores a voltage representing a state of the magnetic memory cell. A second storage device selectively coupled to the magnetic memory cell stores a voltage representing a state of the magnetic memory cell. A differential voltage sense circuit coupled to the first and second storage device that is configured to generate a sensed data output signal for the magnetic memory cell responsive to sensing a difference between voltages stored in the first and second storage devices. A control circuit generates control signals to control the current source to supply current to the magnetic memory cell and to control the coupling of the first and second storage devices to the magnetic memory cell. Magnetic memories and methods are also provided.

Abstract: A memory device includes a memory cell configured to be coupled to complementary first and second bit lines and a differential amplifier having first and second input terminals and operative to amplify a voltage between the first and second input terminals to produce an output signal. First and second voltage-dependent capacitors are coupled to respective ones of the first and second input terminals, and first and second isolation switches are operative to couple and decouple the first and second bit lines to and from respective ones of the first and second voltage-dependent capacitors. The first and second isolation switches may include respective first and second isolation transistors (e.g., NMOS transistors), and the first and second voltage-dependent capacitors may include respective MOS capacitors.

Abstract: Conductive lines are fabricated in integrated circuits by forming a groove in an insulating layer in the integrated circuit, wherein the groove has a sidewall, a base, and an upper surface. An insulating spacer is formed on the sidewall of the groove. The insulating spacer has a sloped contour from the sidewall to the base of the groove, defining a region at the base of the groove that is free of the insulating spacer. A conductive material is formed in the groove extending from the base of the groove to beneath the upper surface of the groove. The sloped contour of the spacer may provide for improved capping of conductive lines by allowing an increase in the amount of conductive material removed by a back-etching process, thereby reducing the likelihood of an electrical short between conductive lines.