Patents by Inventor Giacomo PEDRETTI
Giacomo PEDRETTI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240184479Abstract: A system for facilitating an enhanced k-SAT solver is provided. The system can include a set of analog content addressable memory (aCAM) modules that can represent an expression in a conjunctive normal form (CNF), wherein a respective aCAM module corresponds to a clause of the expression. The system can also include a set of data lines that can provide input candidate values to the set of aCAM modules. A controller of the system can program the set of aCAM modules with respective analog values to represent the expression. The system can also include sensing logic block to determine a distance of a current solution from a target solution based on a combination of respective outputs from the set of aCAM modules. The controller can then iteratively modify an input value for a subset of data lines until the current solution converges based on a convergence condition.Type: ApplicationFiled: January 22, 2024Publication date: June 6, 2024Inventors: Giacomo Pedretti, John Paul Strachan, Thomas Maurits M. Van Vaerenbergh, Catherine E. Graves
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Publication number: 20240170064Abstract: The disclosure generally provides for a method of solving a K-SAT problem. The method comprises programming one or more clauses of a Boolean expression for a K-SAT problem written in negated disjunctive normal form (DNF) to a ternary-CAM (TCAM) array comprising columns and rows of TCAM cells, applying an interpretation comprising one or more binary variables expected to solve the Boolean expression as an input along the columns to the TCAM array, returning a binary value for each clause and updating one or more variables within the interpretation if at least one clause is violated.Type: ApplicationFiled: January 24, 2024Publication date: May 23, 2024Inventors: Giacomo Pedretti, Tobias Frederic Ziegler, Thomas Van Vaerenbergh, Catherine Graves
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Publication number: 20240153555Abstract: Systems and methods are provided for employing analog content addressable memory (aCAMs) to achieve low latency complex distribution sampling. For example, an aCAM core circuit can include an aCAM array. Amplitudes of a probability distribution function are mapped to a width of one or more aCAM cells in each row of the aCAM array. The aCAM core circuit can also include a resistive random access memory (RRAM) storing lookup information, such as information used for processing a model. By randomly selecting columns to search of the aCAM array, the mapped probability distribution function is sampled in a manner that has low latency. The aCAM core circuit can accelerate the sampling step in methods relying on sampling from arbitrary probability distributions, such as particle filter techniques. A hardware architecture for an aCAM Particle Filter that utilizes the aCAM core circuit as a central structure is also described.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Inventors: Catherine Graves, Giacomo Pedretti, Sergey Serebryakov, John Paul Strachan
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Publication number: 20240111490Abstract: Systems and methods are provided for employing a current input analog content addressable memory (CI-aCAM). The CI-aCAM is particularly structured as aCAM that allows the analog signal that is input into the aCAM cell to be received as current. A larger hardware architecture that combines two core analog compute circuits, namely a dot product engine (DPE) circuit for matrix multiplications and an aCAM circuit for search operations can also be realized using the disclosed CI-aCAM. For instance, a DPE circuit, which output current signals, can be directly connected with the input of a CI-aCAM, which is designed to receive current signals in a manner that eliminates conversion steps and circuits (e.g., analog to digital and current to voltage). By leveraging CI-aCAMs, a combined DPE-aCAM hardware architecture can be a realized as a substantially compact structure.Type: ApplicationFiled: September 27, 2022Publication date: April 4, 2024Inventors: CATHERINE GRAVES, GIACOMO PEDRETTI
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Patent number: 11923009Abstract: The disclosure generally provides for a method of solving a K-SAT problem. The method comprises programming one or more clauses of a Boolean expression for a K-SAT problem written in negated disjunctive normal form (DNF) to a ternary-CAM (TCAM) array comprising columns and rows of TCAM cells, applying an interpretation comprising one or more binary variables expected to solve the Boolean expression as an input along the columns to the TCAM array, returning a binary value for each clause and updating one or more variables within the interpretation if at least one clause is violated.Type: GrantFiled: June 15, 2022Date of Patent: March 5, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: Giacomo Pedretti, Tobias Frederic Ziegler, Thomas Van Vaerenbergh, Catherine Graves
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Patent number: 11899965Abstract: A system for facilitating an enhanced k-SAT solver is provided. The system can include a set of analog content addressable memory (aCAM) modules that can represent an expression in a conjunctive normal form (CNF), wherein a respective aCAM module corresponds to a clause of the expression. The system can also include a set of data lines that can provide input candidate values to the set of aCAM modules. A controller of the system can program the set of aCAM modules with respective analog values to represent the expression. The system can also include sensing logic block to determine a distance of a current solution from a target solution based on a combination of respective outputs from the set of aCAM modules. The controller can then iteratively modify an input value for a subset of data lines until the current solution converges based on a convergence condition.Type: GrantFiled: March 10, 2022Date of Patent: February 13, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: Giacomo Pedretti, John Paul Strachan, Thomas Maurits M. Van Vaerenbergh, Catherine E. Graves
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Publication number: 20240046988Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for providing a differentiable content addressable memory (aCAM) that implements an analog input analog storage and analog output learning memory. The analog output of the differentiable CAM can provide input to a learning algorithm, which may compute the gradients in comparison to historic values and reduce data inaccuracies and power consumption.Type: ApplicationFiled: July 28, 2022Publication date: February 8, 2024Inventors: GIACOMO PEDRETTI, Catherine GRAVES, Sergey SEREBRYAKOV, John Paul STRACHAN
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Publication number: 20240047002Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.Type: ApplicationFiled: October 9, 2023Publication date: February 8, 2024Inventors: Giacomo Pedretti, John Paul Strachan, Catherine Graves
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Publication number: 20240029792Abstract: Examples increase precision for aCAMs by converting an input signal (x) received by a circuit into a first analog voltage signal (V(xMSB)) representing the most significant bits of the input signal (x) and a second analog voltage signal (V(xLSB)) representing the least significant bits of the input signal (x). By dividing the input signal (x) bit-wise into the first analog voltage signal (V(xMSB)) and the second analog voltage signal (V(xLSB)), the circuit can utilize aCAM sub-circuits implementing a combination of Boolean operations to search the input signal (x) against 22*M programmable levels, where “M” represents the number of programmable bits for each aCAM sub-circuit. Thus, using similar circuit hardware, example circuits square the number of programmable levels of conventional aCAMs (which generally only have 2M programmable levels). Accordingly, examples provide new aCAMs that can carry out more complex computations than conventional aCAMs of comparable cost, size, and power consumption.Type: ApplicationFiled: July 25, 2022Publication date: January 25, 2024Inventors: TOBIAS FREDERIC ZIEGLER, RON M. ROTH, GIACOMO PEDRETTI, LUCA BUONANNO, PEDRO HENRIQUE ROCHA BRUEL, CATHERINE GRAVES
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Patent number: 11881261Abstract: Systems and methods are provided for employing analog content addressable memory (aCAMs) to achieve low latency complex distribution sampling. For example, an aCAM core circuit can include an aCAM array. Amplitudes of a probability distribution function are mapped to a width of one or more aCAM cells in each row of the aCAM array. The aCAM core circuit can also include a resistive random access memory (RRAM) storing lookup information, such as information used for processing a model. By randomly selecting columns to search of the aCAM array, the mapped probability distribution function is sampled in a manner that has low latency. The aCAM core circuit can accelerate the sampling step in methods relying on sampling from arbitrary probability distributions, such as particle filter techniques. A hardware architecture for an aCAM Particle Filter that utilizes the aCAM core circuit as a central structure is also described.Type: GrantFiled: December 17, 2021Date of Patent: January 23, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: Catherine Graves, Giacomo Pedretti, Sergey Serebryakov, John Paul Strachan
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Publication number: 20230410903Abstract: The disclosure generally provides for a method of solving a K-SAT problem. The method comprises programming one or more clauses of a Boolean expression for a K-SAT problem written in negated disjunctive normal form (DNF) to a ternary-CAM (TCAM) array comprising columns and rows of TCAM cells. The method further includes applying an interpretation comprising one or more binary variables expected to solve the Boolean expression as an input along the columns to the TCAM array, returning a binary value for each clause, randomly selecting one matched match line, determining a selected clause from one or more violated clause, and altering one or more literals within the interpretation using a break count for each variable of the selected clause.Type: ApplicationFiled: June 15, 2022Publication date: December 21, 2023Inventors: GIACOMO PEDRETTI, TOBIAS FREDERIC ZIEGLER, THOMAS VAN VAERENBERGH, CATHERINE GRAVES
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Publication number: 20230410902Abstract: The disclosure generally provides for a method of solving a K-SAT problem. The method comprises programming one or more clauses of a Boolean expression for a K-SAT problem written in negated disjunctive normal form (DNF) to a ternary-CAM (TCAM) array comprising columns and rows of TCAM cells, applying an interpretation comprising one or more binary variables expected to solve the Boolean expression as an input along the columns to the TCAM array, returning a binary value for each clause and updating one or more variables within the interpretation if at least one clause is violated.Type: ApplicationFiled: June 15, 2022Publication date: December 21, 2023Inventors: Giacomo Pedretti, Tobias Frederic Ziegler, Thomas Van Vaerenbergh, Catherine Graves
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Patent number: 11783907Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.Type: GrantFiled: October 29, 2021Date of Patent: October 10, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Giacomo Pedretti, John Paul Strachan, Catherine Graves
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Patent number: 11763888Abstract: Systems and methods provide new circuits that increase aCAM precision by leveraging the concept of range segmenting to representationally store an analog voltage range across multiple aCAM cells/sub-circuits (here the representationally stored analog voltage range may correspond to a word entry). In this way, a circuit of the presently disclosed technology can increase precision (e.g., the number of programmable levels that can be used to store a word entry and/or the number of programmable levels that an input signal can be search against) linearly with each aCAM cell/sub-circuit added to the circuit. Accordingly, circuits of the presently disclosed technology can be used to carry out more complex computations than conventional aCAMs—and thus can be used in a wider range of computational applications.Type: GrantFiled: July 25, 2022Date of Patent: September 19, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Giacomo Pedretti, John Moon, Pedro Henrique Rocha Bruel, Catherine Graves
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Publication number: 20230289090Abstract: A system for facilitating an enhanced k-SAT solver is provided. The system can include a set of analog content addressable memory (aCAM) modules that can represent an expression in a conjunctive normal form (CNF), wherein a respective aCAM module corresponds to a clause of the expression. The system can also include a set of data lines that can provide input candidate values to the set of aCAM modules. A controller of the system can program the set of aCAM modules with respective analog values to represent the expression. The system can also include sensing logic block to determine a distance of a current solution from a target solution based on a combination of respective outputs from the set of aCAM modules. The controller can then iteratively modify an input value for a subset of data lines until the current solution converges based on a convergence condition.Type: ApplicationFiled: March 10, 2022Publication date: September 14, 2023Inventors: Giacomo Pedretti, John Paul Strachan, Thomas Maurits M. Van Vaerenbergh, Catherine E. Graves
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Publication number: 20230197151Abstract: Systems and methods are provided for employing analog content addressable memory (aCAMs) to achieve low latency complex distribution sampling. For example, an aCAM core circuit can include an aCAM array. Amplitudes of a probability distribution function are mapped to a width of one or more aCAM cells in each row of the aCAM array. The aCAM core circuit can also include a resistive random access memory (RRAM) storing lookup information, such as information used for processing a model. By randomly selecting columns to search of the aCAM array, the mapped probability distribution function is sampled in a manner that has low latency. The aCAM core circuit can accelerate the sampling step in methods relying on sampling from arbitrary probability distributions, such as particle filter techniques. A hardware architecture for an aCAM Particle Filter that utilizes the aCAM core circuit as a central structure is also described.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Inventors: CATHERINE GRAVES, GIACOMO PEDRETTI, SERGEY SEREBRYAKOV, JOHN PAUL STRACHAN
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Publication number: 20230137079Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.Type: ApplicationFiled: October 29, 2021Publication date: May 4, 2023Inventors: GIACOMO PEDRETTI, JOHN PAUL STRACHAN, CATHERINE GRAVES
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Patent number: 11314843Abstract: It is described a mathematical solving circuit (100) comprising: a crosspoint matrix (MG) including a plurality of row conductors (Li), a plurality of column conductors (Cj) and a plurality of analog resistive memories (Gij), each connected between a row conductor and a column conductor; a plurality of operational amplifiers (OAi) each having: a first input terminal (IN1i) connected to a respective row conductor (Li), a second input terminal (IN2i) connected to a ground terminal (GR) at least one operational amplifier (OAi) of the plurality being such to take the respective first input terminal (IN1i) to a virtual ground.Type: GrantFiled: September 27, 2018Date of Patent: April 26, 2022Inventors: Daniele Ielmini, Zhong Sun, Giacomo Pedretti
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Publication number: 20200233922Abstract: It is described a mathematical solving circuit (100) comprising: a crosspoint matrix (MG) including a plurality of row conductors (Li), a plurality of column conductors (Cj) and a plurality of analog resistive memories (Gij), each connected between a row conductor and a column conductor; a plurality of operational amplifiers (OAi) each having: a first input terminal (IN1i) connected to a respective row conductor (Li), a second input terminal (IN2i) connected to a ground terminal (GR) at least one operational amplifier (OAi) of the plurality being such to take the respective first input terminal (IN1i) to a virtual ground.Type: ApplicationFiled: September 27, 2018Publication date: July 23, 2020Inventors: Daniele IELMINI, Zhong SUN, Giacomo PEDRETTI