Patents by Inventor Gian-Paolo D. Musumeci

Gian-Paolo D. Musumeci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6988156
    Abstract: A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface. An interrupt handler adjusts dynamic Packet and/or Latency values to control how many packets the interface may accumulate, or how much time the interface may wait after receiving a first packet, before it can signal a corresponding interrupt to a host processor and forward the accumulated packet(s). The interrupt handler maintains a Trend parameter reflecting a comparison between recent sets of packets received from the interface and the Packet parameter. The Packet value is decreased or increased as packet traffic ebbs or flows. When the Packet value is incremented from a minimum value, a Fallback mechanism may be activated to ensure a relatively rapid return to the minimum value if an insufficient amount of traffic is received to warrant a non-minimum Packet value. The Latency value may be increased as the processor's workload increases.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: January 17, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Gian-Paolo D. Musumeci
  • Patent number: 6920530
    Abstract: A method and system for storing instructions retrieved from memory in a memory cache to provide said instructions to a processor. First a new instruction is received from the memory. The system then determines whether the new instruction is a start of a basic block of instructions. If the new instruction is the start of a basic block of instructions, the system determines whether the basic block of instructions is stored in the memory cache responsive. If the basic block of instructions is not stored in the memory cache, the system retrieves the basic block of instructions for the new instruction from the memory. The system then stores the basic block of instructions in a buffer. The system then predicts a next basic block of instructions needed by the processor from the basic block of instructions.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: July 19, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Gian-Paolo D. Musumeci
  • Patent number: 6889277
    Abstract: A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface to suit the workload of the interface. An interrupt handler adjusts dynamic Packet and/or Latency values of the interface to control how many packets the interface may accumulate, or how much time the interface may wait after receiving a first packet, before it can signal a corresponding interrupt to a host processor and forward the accumulated packet(s). The interrupt handler maintains a Trend parameter reflecting a comparison between recent sets of packets received from the interface and the interface's Packet parameter. The Packet value is decreased or increased as packet traffic ebbs or flows. When the Packet value is incremented from a minimum value, a Fallback mechanism may be activated to ensure a relatively rapid return to the minimum value if an insufficient amount of traffic is received to warrant a non-minimum Packet value.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: May 3, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Gian-Paolo D. Musumeci
  • Patent number: 6865649
    Abstract: A system and method for pre-fetching data. A computer program comprising multiple basic blocks is submitted to a processor for execution. Tables or other data structures are associated with some or all of the basic blocks (e.g., a table is associated with, or stores, an instruction address of a particular basic block). During execution of a basic block, memory locations of data elements accessed during the executions are stored in the associated table. After a threshold number of executions, differences between memory locations of the data elements in successive executions are then computed. The differences are applied to the last stored memory locations to generate estimates of the locations for the data elements for a subsequent execution. Using the estimated locations, the data elements can be pre-fetched before, or as, the basic block is executed.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: March 8, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Gian-Paolo D. Musumeci
  • Publication number: 20040073752
    Abstract: A system and method for pre-fetching data. A computer program comprising multiple basic blocks is submitted to a processor for execution. Tables or other data structures are associated with some or all of the basic blocks (e.g., a table is associated with, or stores, an instruction address of a particular basic block). During execution of a basic block, memory locations of data elements accessed during the executions are stored in the associated table. After a threshold number of executions, differences between memory locations of the data elements in successive executions are then computed. The differences are applied to the last stored memory locations to generate estimates of the locations for the data elements for a subsequent execution. Using the estimated locations, the data elements can be pre-fetched before, or as, the basic block is executed.
    Type: Application
    Filed: October 10, 2002
    Publication date: April 15, 2004
    Inventor: Gian-Paolo D. Musumeci
  • Publication number: 20030200369
    Abstract: A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface. An interrupt handler adjusts dynamic Packet and/or Latency values to control how many packets the interface may accumulate, or how much time the interface may wait after receiving a first packet, before it can signal a corresponding interrupt to a host processor and forward the accumulated packet(s). The interrupt handler maintains a Trend parameter reflecting a comparison between recent sets of packets received from the interface and the Packet parameter. The Packet value is decreased or increased as packet traffic ebbs or flows. When the Packet value is incremented from a minimum value, a Fallback mechanism may be activated to ensure a relatively rapid return to the minimum value if an insufficient amount of traffic is received to warrant a non-minimum Packet value. The Latency value may be increased as the processor's workload increases.
    Type: Application
    Filed: October 10, 2002
    Publication date: October 23, 2003
    Inventor: Gian-Paolo D. Musumeci
  • Publication number: 20030200396
    Abstract: A method and system for storing instructions retrieved from memory in a memory cache to provide said instructions to a processor. First a new instruction is received from the memory. The system then determines whether the new instruction is a start of a basic block of instructions. If the new instruction is the start of a basic block of instructions, the system determines whether the basic block of instructions is stored in the memory cache responsive. If the basic block of instructions is not stored in the memory cache, the system retrieves the basic block of instructions for the new instruction from the memory. The system then stores the basic block of instructions in a buffer. The system then predicts a next basic block of instructions needed by the processor from the basic block of instructions.
    Type: Application
    Filed: April 23, 2002
    Publication date: October 23, 2003
    Applicant: Sun Microsystems, Inc.
    Inventor: Gian-Paolo D. Musumeci
  • Publication number: 20030200368
    Abstract: A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface to suit the workload of the interface. An interrupt handler adjusts dynamic Packet and/or Latency values of the interface to control how many packets the interface may accumulate, or how much time the interface may wait after receiving a first packet, before it can signal a corresponding interrupt to a host processor and forward the accumulated packet(s). The interrupt handler maintains a Trend parameter reflecting a comparison between recent sets of packets received from the interface and the interface's Packet parameter. The Packet value is decreased or increased as packet traffic ebbs or flows. When the Packet value is incremented from a minimum value, a Fallback mechanism may be activated to ensure a relatively rapid return to the minimum value if an insufficient amount of traffic is received to warrant a non-minimum Packet value.
    Type: Application
    Filed: April 18, 2002
    Publication date: October 23, 2003
    Inventor: Gian-Paolo D. Musumeci