Patents by Inventor Gianfranco Valeri
Gianfranco Valeri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11842774Abstract: Memory might include a controller configured to determine, for each sense circuit of a plurality of sense circuits, a respective plurality of first logic levels for that sense circuit while capacitively coupling a respective plurality of voltage levels to its respective sense node, to determine a particular voltage level in response to each respective plurality of first logic levels for the plurality of sense circuits and their respective plurality of voltage levels, and to determine, for each sense circuit of the plurality of sense circuits, a respective second logic level for that sense circuit while capacitively coupling the particular voltage level to its respective sense node.Type: GrantFiled: January 25, 2022Date of Patent: December 12, 2023Assignee: Micron Technology, Inc.Inventors: Gianfranco Valeri, Violante Moschiano, Walter Di-Francesco
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Publication number: 20230134281Abstract: A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled to the array of memory cells. The control logic performs operations including: causing hardware initialization of a set of sub-blocks that are to be programmed within the array of memory cells; causing a first sub-block of the set of sub-blocks to be preconditioned for a program operation; causing multiple pages of data to be programmed to respective ones of the set of sub-blocks; and selectively causing a program verify to be performed on memory cells of the set of sub-blocks after programming the multiple pages of data.Type: ApplicationFiled: October 28, 2022Publication date: May 4, 2023Inventors: Leo Raimondo, Federica Paolini, Umberto Siciliani, Violante Moschiano, Gianfranco Valeri, Davide Esposito, Walter Di Francesco
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Patent number: 11416154Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.Type: GrantFiled: December 16, 2020Date of Patent: August 16, 2022Assignee: Micron Technology, Inc.Inventors: Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Walter Di Francesco, Vamshi K. Indavarapu, Gianfranco Valeri, Renato C. Padilla, Ali Mohammadzadeh, Jung Sheng Hoei, Luca De Santis
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Publication number: 20220148661Abstract: Memory might include a controller configured to determine, for each sense circuit of a plurality of sense circuits, a respective plurality of first logic levels for that sense circuit while capacitively coupling a respective plurality of voltage levels to its respective sense node, to determine a particular voltage level in response to each respective plurality of first logic levels for the plurality of sense circuits and their respective plurality of voltage levels, and to determine, for each sense circuit of the plurality of sense circuits, a respective second logic level for that sense circuit while capacitively coupling the particular voltage level to its respective sense node.Type: ApplicationFiled: January 25, 2022Publication date: May 12, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Gianfranco Valeri, Violante Moschiano, Walter Di-Francesco
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Patent number: 11270774Abstract: Memory might include controller configured to apply a first predetermined voltage level to a capacitance of a sense circuit during a first sensing stage of a sensing operation, determine a first value of an output of the particular sense circuit while applying the first predetermined voltage level, apply a second predetermined voltage level to the capacitance during a second sensing stage of the sensing operation, determine a second value of the output of the particular sense circuit while applying the second predetermined voltage level, determine a particular voltage level in response to at least the first value and the second value, and apply the particular voltage level to the capacitance during a final sensing stage of the sensing operation.Type: GrantFiled: October 26, 2020Date of Patent: March 8, 2022Assignee: Micron Technology, Inc.Inventors: Gianfranco Valeri, Violante Moschiano, Walter Di-Francesco
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Publication number: 20210103389Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.Type: ApplicationFiled: December 16, 2020Publication date: April 8, 2021Inventors: Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Walter Di Francesco, Vamshi K. Indavarapu, Gianfranco Valeri, Renato C. Padilla, Ali Mohammadzadeh, Jung Sheng Hoei, Luca De Santis
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Publication number: 20210043262Abstract: Memory might include controller configured to apply a first predetermined voltage level to a capacitance of a sense circuit during a first sensing stage of a sensing operation, determine a first value of an output of the particular sense circuit while applying the first predetermined voltage level, apply a second predetermined voltage level to the capacitance during a second sensing stage of the sensing operation, determine a second value of the output of the particular sense circuit while applying the second predetermined voltage level, determine a particular voltage level in response to at least the first value and the second value, and apply the particular voltage level to the capacitance during a final sensing stage of the sensing operation.Type: ApplicationFiled: October 26, 2020Publication date: February 11, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Gianfranco Valeri, Violante Moschiano, Walter Di-Francesco
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Patent number: 10877679Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.Type: GrantFiled: May 31, 2019Date of Patent: December 29, 2020Assignee: Micron Technology, Inc.Inventors: Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Walter Di Francesco, Vamshi K. Indavarapu, Gianfranco Valeri, Renato C. Padilla, Ali Mohammadzadeh, Jung Sheng Hoei, Luca De Santis
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Publication number: 20200365214Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining first states of a first sense node and a second sense node while a first voltage level is capacitively coupled to the first sense node and while a second voltage level is capacitively coupled to the second sense node, determining a second states of the first and second sense nodes while a third voltage level is capacitively coupled to the first sense node and while a fourth voltage level is capacitively coupled to the second sense node, determining a fifth voltage level in response to at least the first states of the first and second sense nodes and the second states of the first and second sense nodes, and determining third states of the first and second sense nodes while the fifth voltage level is capacitively coupled to the first and second sense nodes.Type: ApplicationFiled: May 17, 2019Publication date: November 19, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Gianfranco Valeri, Violante Moschiano, Walter Di-Francesco
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Patent number: 10818363Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining first states of a first sense node and a second sense node while a first voltage level is capacitively coupled to the first sense node and while a second voltage level is capacitively coupled to the second sense node, determining a second states of the first and second sense nodes while a third voltage level is capacitively coupled to the first sense node and while a fourth voltage level is capacitively coupled to the second sense node, determining a fifth voltage level in response to at least the first states of the first and second sense nodes and the second states of the first and second sense nodes, and determining third states of the first and second sense nodes while the fifth voltage level is capacitively coupled to the first and second sense nodes.Type: GrantFiled: May 17, 2019Date of Patent: October 27, 2020Assignee: Micron Technolgy, Inc.Inventors: Gianfranco Valeri, Violante Moschiano, Walter Di-Francesco
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Patent number: 10423350Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.Type: GrantFiled: January 23, 2017Date of Patent: September 24, 2019Assignee: Micron Technology, Inc.Inventors: Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Walter Di Francesco, Vamshi K. Indavarapu, Gianfranco Valeri, Renato C. Padilla, Ali Mohammadzadeh, Jung Sheng Hoei, Luca De Santis
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Publication number: 20190286328Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.Type: ApplicationFiled: May 31, 2019Publication date: September 19, 2019Inventors: Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Walter Di Francesco, Vamshi K. Indavarapu, Gianfranco Valeri, Renato C. Padilla, Ali Mohammadzadeh, Jung Sheng Hoei, Luca De Santis
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Patent number: 10359963Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.Type: GrantFiled: January 23, 2017Date of Patent: July 23, 2019Assignee: Micron Technology, Inc.Inventors: Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Walter Di Francesco, Vamshi K. Indavarapu, Gianfranco Valeri, Renato C. Padilla, Ali Mohammadzadeh, Jung Sheng Hoei, Luca De Santis
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Publication number: 20180210653Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.Type: ApplicationFiled: January 23, 2017Publication date: July 26, 2018Inventors: Sivagnanam Parthasarathy, Terry M. Grunzke, Lucia Botticchio, Walter Di Francesco, Vamshi K. Indavarapu, Gianfranco Valeri, Renato C. Padilla, Ali Mohammadzadeh, Jung Sheng Hoei, Luca De Santis