Abstract: A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.

Abstract: A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.

Abstract: An integrated image processing system includes an array of cells arranged in rows and columns. Each cell corresponds to a pixel of an image and includes a photosensitive element for detecting the luminous intensity of its respective pixel and for generating a value. A first switch controls the transfer of the value from a respective photosensitive element to the corresponding capacitor, which stores the value. A second switch couples each of the cells in parallel to a common line. A control circuit receives the values from each cell on the common line and generates a signal for regulating the switching time interval of the first switch.

Abstract: A voltage regulator (400) having a charge pump includes a bias current circuit (402) which produces a bias current (I.sub.bias). The bias current (I.sub.bias) is mirrored by a first mirror circuit (404) and multiplied by gain stage Q4.sub.beta and mirrored again by a factor "c" on the output of DMOS2. The same I.sub.bias is mirrored by a ratio "b" and multiplied by the product of Q5.sub.beta and Q6.sub.beta. The push-pull current operation at the output terminal (416) is obtained by turning on and off switches SW1 (418) and SW2 (420) that are controlled by a clock signal. The voltage regulator (400) further includes an output voltage clamp (424) that keeps control of the V.sub.boost voltage by controlling the amount of bias current (I.sub.bias).

Abstract: A circuit and method to clamp a node of a power device connected to a driving node of a polyphase d-c motor to a reference potential during a powering off of the drive includes a current mirror and a comparator. A first input of the comparator is connected to the reference potential, and a second input is connected to the driving node. The reference potential may be a ground potential, or, preferably, the potential at another driving node of the motor. An output of the comparator is connected to a first side of the current mirror. A circuit is connected to apply a current reflecting the output of the comparator to a low side driver connected to the node.

Abstract: A driver circuit with an amplifier operated in a switching mode has threshold detectors with devices to compare the amplifier input and output voltage respectively to predetermined minimum and maximum levels representing fully off and fully on conditions for the driver circuit. The circuit provides signals to enable the amplifier to draw current from a supply only during transitions between the threshold levels and to otherwise disable the amplifier. The circuit is beneficial particularly when operating the amplifier from a voltage supply of very limited current capability, such as a charge pump voltage in an integrated circuit. The switching mode amplifier can be applied in high performance driver integrated circuits alone or in combination with innovative techniques for slew rate control and for preslewing the amplifier output that also provide high performance in compact circuit configurations.

Abstract: A voltage ramp generator for a driver circuit is provided to give an output that is highly linear between zero and a maximum voltage has a combination of current sources or generators for charging and discharging a capacitor, with discharging performed by sequencing two different types of current sources. A first current source on the discharge side of the capacitor has transistors in cascode connected current mirrors and takes the capacitor voltage to a low value but not as low as zero. A second current source of a basic or simple current mirror then takes the capacitor voltage substantially to zero. The voltage ramp generator meets the requirements of high performance, integrated, driver circuits, particularly for achieving complete turn-off of a power device such as a DMOS transistor in a high side cascoded transistors goes up to a threshold near the full supply driver.

Abstract: A multiplier presenting four multiplying branches, each formed by a buffer transistor and by two input transistors arranged in series to one another and connected between two output nodes and a common node. A biasing branch presents a diode-connected forcing transistor with its gate terminal connected to the gate terminal of all the buffer transistors, and its source terminal connected to the common node. The forcing transistor forces the input transistors to operate in the triode (linear) region, i.e., as voltage-controlled resistors, so that they conduct a current linearly proportional to the voltage drop between the respective source and gate terminals, and the currents through the output nodes are proportional to the input voltages applied to the control terminals of the input transistors. By cross-coupling the multiplying branches to the output nodes and subtracting the two output currents, a current is obtained which is proportional to the product of the two input voltages.

Abstract: A method and a respective circuit arrangement capable of markedly limiting the absorption of current by a current comparator circuit. The invention consists in limiting the absorption of current through the branch of the comparator circuit, along which is forced the highest current to the value of the lowest current, which is in turn forced through the other branch of the comparator circuit. This condition is obtained without interfering in any way with other characteristics of switching speed and sensitivity of the comparator circuit.

Abstract: A preslewing circuit to rapidly drop a voltage on the gate of a power device in a power stage has a combination of a bipolar transistor and CMOS transistors. The gate voltage is brought down by the preslewing circuit to a level at which an output voltage can begin to change. The combination has high conduction and can be integrated readily, with good internal isolation, in a small chip area, thus having qualities desirable for high performance, integrated, driver circuits.

Abstract: An analog multiplier circuit includes three transconductance stages. One of the transconductance stages, receiving a first differential voltage, conducts a differential current responsive to the first differential voltage from the other two transconductance stages. The differential current changes the transconductance in the other two transconductance stages, which are cross-coupled with one another. The second differential input voltage is presented to the other two transconductance stages in parallel, resulting in an output differential current or voltage based on the product of the first and second differential input voltages. Each of the transconductance stages is implemented in BiCMOS, and each includes two differential legs, each having a MOS transistor receiving an input signal and a cascode bipolar transistor.

Abstract: A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.