Patents by Inventor Gianni S. Alsasua
Gianni S. Alsasua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11782627Abstract: A processing device in a memory system receives a first read request from a host system, wherein the first read request is directed to first data stored at a first address in a block of the memory component. The processing device determines that the first address is located within a first region of the block and increments a read counter for the block by a default amount. The processing device further receives a second read request from the host system, wherein the second read request is directed to second data stored at a second address in a block of the memory component, determines that the second address is located within a second region of the block and increments the read counter for the block by a scaled amount.Type: GrantFiled: February 25, 2022Date of Patent: October 10, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Harish R. Singidi, Gianni S. Alsasua
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Patent number: 11682446Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing a first data integrity check on memory pages of a first set of wordlines of the memory device; performing a second data integrity check on memory pages of a second set of wordlines comprising a plurality of wordlines from the first set of wordlines; identifying, among the first set of wordlines and the second set of wordlines, a wordline having a first data state metric value obtained from the first data integrity check equal to a second data state metric value obtained from the second data integrity check; and performing a third data integrity check on a third set of wordlines comprising at least one wordline from the first set of wordlines, wherein the third data integrity check excludes the identified wordline.Type: GrantFiled: February 24, 2022Date of Patent: June 20, 2023Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
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Publication number: 20230059923Abstract: A trigger rate associated with a scan operation of a set of memory pages of a data block is identified. The trigger rate is compared to a threshold rate to determine that a condition is satisfied. In response to satisfying the condition, a refresh operation is executed on the set of memory pages of the data block.Type: ApplicationFiled: November 3, 2022Publication date: February 23, 2023Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Ashutosh Malshe, Gianni S. Alsasua, Harish R. Singidi
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Patent number: 11521699Abstract: A first scan operation of a set of memory pages of a data block is performed using a first reliability threshold level to identify a set of scan results. A workload type associated with the data block is determined based on the set of scan results. The first reliability threshold level is adjusted to a second reliability threshold level based on the workload type. A second scan operation of the set of memory pages of the data block is performed using the second reliability threshold level.Type: GrantFiled: October 30, 2020Date of Patent: December 6, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Ashutosh Malshe, Gianni S. Alsasua, Harish R. Singidi
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Publication number: 20220180922Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing a first data integrity check on memory pages of a first set of wordlines of the memory device; performing a second data integrity check on memory pages of a second set of wordlines comprising a plurality of wordlines from the first set of wordlines; identifying, among the first set of wordlines and the second set of wordlines, a wordline having a first data state metric value obtained from the first data integrity check equal to a second data state metric value obtained from the second data integrity check; and performing a third data integrity check on a third set of wordlines comprising at least one wordline from the first set of wordlines, wherein the third data integrity check excludes the identified wordline.Type: ApplicationFiled: February 24, 2022Publication date: June 9, 2022Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
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Publication number: 20220179577Abstract: A processing device in a memory system receives a first read request from a host system, wherein the first read request is directed to first data stored at a first address in a block of the memory component. The processing device determines that the first address is located within a first region of the block and increments a read counter for the block by a default amount. The processing device further receives a second read request from the host system, wherein the second read request is directed to second data stored at a second address in a block of the memory component, determines that the second address is located within a second region of the block and increments the read counter for the block by a scaled amount.Type: ApplicationFiled: February 25, 2022Publication date: June 9, 2022Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Harish R. Singidi, Gianni S. Alsasua
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Publication number: 20220139481Abstract: A first scan operation of a set of memory pages of a data block is performed using a first reliability threshold level to identify a set of scan results. A workload type associated with the data block is determined based on the set of scan results. The first reliability threshold level is adjusted to a second reliability threshold level based on the workload type. A second scan operation of the set of memory pages of the data block is performed using the second reliability threshold level.Type: ApplicationFiled: October 30, 2020Publication date: May 5, 2022Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Ashutosh Malshe, Gianni S. Alsasua, Harish R. Singidi
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Patent number: 11301146Abstract: A memory block of a non-volatile memory device is identified. The memory block has a first region and a second region, where a storage density of the first region is larger than the second region. Data is programmed at the first region of the memory block. An attribute of the memory block based on a sensor is received during programming of the data at the memory block. The attribute characterizes the data being programmed at the first region. The attribute is stored at a volatile during programming of the data at the memory block. The attribute is stored on a memory page of the second region responsive to the programming of the data at the first region being complete.Type: GrantFiled: June 1, 2020Date of Patent: April 12, 2022Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
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Patent number: 11287998Abstract: A processing device in a memory system receives a first read request from a host system, wherein the first read request is directed to first data stored at a first address in a block of the memory component. The processing device determines that the first address is located within a first region of the block and increments a read counter for the block by a default amount. The processing device further receives a second read request from the host system, wherein the second read request is directed to second data stored at a second address in a block of the memory component, determines that the second address is located within a second region of the block and increments the read counter for the block by a scaled amount.Type: GrantFiled: August 2, 2019Date of Patent: March 29, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Harish R. Singidi, Gianni S. Alsasua
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Patent number: 11282564Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including identifying, among a first plurality of wordlines of a set of pages of the memory device, at least one wordline having a current value of a data state metric satisfying a first condition; determining new values of the data state metric of a second plurality of wordlines of the set of pages, wherein the at least one wordline is excluded from the second plurality of wordlines; and responsive to determining that the new values of the data state metric of one or more wordlines of the second plurality of wordlines satisfy a second condition, performing a media management operation with respect to the one or more wordlines.Type: GrantFiled: November 11, 2020Date of Patent: March 22, 2022Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
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Patent number: 11200957Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on at least one of a physical block or a plurality of physical blocks of a memory device, wherein the counter is associated with the physical block or the plurality of physical blocks depending on an age of data stored on the physical block. The processing device further determines whether a value of the counter satisfies a first threshold criterion pertaining to the number of read operations performed, and responsive to the value of the counter satisfying the first threshold criterion, performs a data integrity scan to determine a first error rate.Type: GrantFiled: February 19, 2021Date of Patent: December 14, 2021Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Ashutosh Malshe, Harish R. Singidi, Gianni S. Alsasua
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Publication number: 20210191815Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on at least one of a physical block or a plurality of physical blocks of a memory device, wherein the counter is associated with the physical block or the plurality of physical blocks depending on an age of data stored on the physical block. The processing device further determines whether a value of the counter satisfies a first threshold criterion pertaining to the number of read operations performed, and responsive to the value of the counter satisfying the first threshold criterion, performs a data integrity scan to determine a first error rate.Type: ApplicationFiled: February 19, 2021Publication date: June 24, 2021Inventors: Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Ashutosh Malshe, Harish R. Singidi, Gianni S. Alsasua
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Patent number: 10950317Abstract: A processing device in a memory system determines that data stored in a first block of a plurality of blocks of a memory component satisfies a first threshold criterion pertaining to an age of the data. Responsive to the data stored in the first block satisfying the first threshold criterion, the processing device maintains a first counter to track a number of read operations performed on the first block. The processing device further determines that the data stored in the first block does not satisfy the first threshold criterion, and in response, maintains a second counter to track a number of read operations performed on a super block comprising the plurality of blocks.Type: GrantFiled: August 2, 2019Date of Patent: March 16, 2021Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Ashutosh Malshe, Harish R. Singidi, Gianni S. Alsasua
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Publication number: 20210034274Abstract: A processing device in a memory system receives a first read request from a host system, wherein the first read request is directed to first data stored at a first address in a block of the memory component. The processing device determines that the first address is located within a first region of the block and increments a read counter for the block by a default amount. The processing device further receives a second read request from the host system, wherein the second read request is directed to second data stored at a second address in a block of the memory component, determines that the second address is located within a second region of the block and increments the read counter for the block by a scaled amount.Type: ApplicationFiled: August 2, 2019Publication date: February 4, 2021Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Vamsi Pavan Rayaprolu, Harish R. Singidi, Gianni S. Alsasua
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Publication number: 20210035649Abstract: A processing device in a memory system determines that data stored in a first block of a plurality of blocks of a memory component satisfies a first threshold criterion pertaining to an age of the data. Responsive to the data stored in the first block satisfying the first threshold criterion, the processing device maintains a first counter to track a number of read operations performed on the first block. The processing device further determines that the data stored in the first block does not satisfy the first threshold criterion, and in response, maintains a second counter to track a number of read operations performed on a super block comprising the plurality of blocks.Type: ApplicationFiled: August 2, 2019Publication date: February 4, 2021Inventors: Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Ashutosh Malshe, Harish R. Singidi, Gianni S. Alsasua
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Publication number: 20200293203Abstract: A memory block of a non-volatile memory device is identified. The memory block has a first region and a second region, where a storage density of the first region is larger than the second region. Data is programmed at the first region of the memory block. An attribute of the memory block based on a sensor is received during programming of the data at the memory block. The attribute characterizes the data being programmed at the first region. The attribute is stored at a volatile during programming of the data at the memory block. The attribute is stored on a memory page of the second region responsive to the programming of the data at the first region being complete.Type: ApplicationFiled: June 1, 2020Publication date: September 17, 2020Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
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Patent number: 10671298Abstract: Data to store at a storage system is received. The storage system includes data blocks and the plurality of blocks that include a first region corresponding to a first storage density and a second region corresponding to a second storage density that is less dense than the first storage density. The data is stored at the first region of the plurality of data blocks that corresponds to the first storage density. A write attribute related to storing the data at the first region of the plurality of data blocks is determined. Thereupon, the write attribute related to storing the data at the first region is stored in the second region of the plurality of data blocks that corresponds to the second storage density.Type: GrantFiled: March 6, 2018Date of Patent: June 2, 2020Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
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Patent number: 10510422Abstract: Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.Type: GrantFiled: September 10, 2018Date of Patent: December 17, 2019Assignee: Micron Technology, Inc.Inventors: Gary F. Besinga, Peng Fei, Michael G. Miller, Roland J. Awusie, Kishore Kumar Muchherla, Renato C. Padilla, Harish R. Singidi, Jung Sheng Hoei, Gianni S. Alsasua
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Publication number: 20190278491Abstract: Data to store at a storage system is received. The storage system includes data blocks and the plurality of blocks that include a first region corresponding to a first storage density and a second region corresponding to a second storage density that is less dense than the first storage density. The data is stored at the first region of the plurality of data blocks that corresponds to the first storage density. A write attribute related to storing the data at the first region of the plurality of data blocks is determined. Thereupon, the write attribute related to storing the data at the first region is stored in the second region of the plurality of data blocks that corresponds to the second storage density.Type: ApplicationFiled: March 6, 2018Publication date: September 12, 2019Inventors: Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Kishore Kumar Muchherla, Harish R. Singidi, Ashutosh Malshe, Gianni S. Alsasua
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Publication number: 20190043592Abstract: Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.Type: ApplicationFiled: September 10, 2018Publication date: February 7, 2019Inventors: Gary F. Besinga, Peng Fei, Michael G. Miller, Roland J. Awusie, Kishore Kumar Muchherla, Renato C. Padilla, Harish R. Singidi, Jung Sheng Hoei, Gianni S. Alsasua