Abstract: A network device includes a packet processor, a plurality of interface circuits, a phase-locked loop (PLL) circuit and a configuration controller. The interface circuits are configured to transmit and receive signals to/from other devices that are coupled to the network device. A master interface circuit among the interface circuits is configured to recover a network clock from a received signal. The PLL circuit is configured to generate an interface clock based on a system clock of the network device and a configuration of the PLL circuit and to provide the interface clock to the plurality of interface circuits to govern communication timings of the interface circuits. The configuration controller is configured to detect a difference of the interface clock relative to the recovered network clock, and to determine the configuration of the PLL circuit based on the difference to govern operation of the PLL circuit.

Abstract: Aspects of the disclosure provide a circuit having a pulse latch circuit and an enable circuit. The latch circuit is configured to receive a first signal at an input lead and drive the first signal to an output lead in response to an enable signal. The enable circuit is configured to be active to generate the enable signal to enable the latch circuit to receive the first signal when the first signal is different from a second signal on the output lead and is configured to default the enable signal to suppress the first signal so as not to be received at the latch circuit when the first signal is the same as the second signal.

Abstract: Systems and methods are provided for determining a clock time associated with an event at a higher precision than is attainable by a main clock signal. A system includes a plurality of processing modules distributed across an integrated circuit, a main clock signal being transmitted to ones of the plurality of processing modules at a main clock frequency. A plurality of sub-cycle frequency resolution modules are disposed in corresponding ones of the processing modules, the sub-cycle frequency modules generating sub-cycle phase indicators at a frequency that is greater than the main clock frequency, the sub-cycle frequency resolution modules being configured to receive the main clock signal and to determine a clock time of an event based on a combination of the main clock and the sub-cycle phase indicators.

Abstract: Aspects of the disclosure provide a data storage circuit. The data storage circuit includes a first latch, a second latch, and a clock gating and buffer circuit. The first latch is configured to provide an intermediate output to the second latch in response to a data input when a clock signal is in a first state and to hold the intermediate output when the clock signal is in a second state, and the second latch is configured to provide a data output in response to the intermediate output and the clock signal. The clock gating and buffer circuit is configured to provide the clock signal, and to suppress providing the clock signal to one or both of the first latch and the second latch when the intermediate output stays unchanged.

Abstract: A network device includes a packet processor, a plurality of interface circuits, a phase-locked loop (PLL) circuit and a configuration controller. The interface circuits are configured to transmit and receive signals to/from other devices that are coupled to the network device. A master interface circuit among the interface circuits is configured to recover a network clock from a received signal. The PLL circuit is configured to generate an interface clock based on a system clock of the network device and a configuration of the PLL circuit and to provide the interface clock to the plurality of interface circuits to govern communication timings of the interface circuits. The configuration controller is configured to detect a difference of the interface clock relative to the recovered network clock, and to determine the configuration of the PLL circuit based on the difference to govern operation of the PLL circuit.

Abstract: Aspects of the disclosure provide a data storage circuit. The data storage circuit includes a first latch, a second latch, and a clock gating and buffer circuit. The first latch is configured to provide an intermediate output to the second latch in response to a data input when a clock signal is in a first state and to hold the intermediate output when the clock signal is in a second state, and the second latch is configured to provide a data output in response to the intermediate output and the clock signal. The clock gating and buffer circuit is configured to provide the clock signal, and to suppress providing the clock signal to one or both of the first latch and the second latch when the intermediate output stays unchanged.

Abstract: Aspects of the disclosure provide a data storage circuit. The data storage circuit includes a first latch, a second latch, and a clock gating and buffer circuit. The first latch is configured to provide an intermediate output to the second latch in response to a data input when a clock signal is in a first state and to hold the intermediate output when the clock signal is in a second state, and the second latch is configured to provide a data output in response to the intermediate output and the clock signal. The clock gating and buffer circuit is configured to provide the clock signal, and to suppress providing the clock signal to one or both of the first latch and the second latch when the intermediate output stays unchanged.

Abstract: Aspects of the disclosure provide a circuit having a pulse latch circuit and an enable circuit. The latch circuit is configured to receive a first signal at an input lead and drive the first signal to an output lead in response to an enable signal. The enable circuit is configured to be active to generate the enable signal to enable the latch circuit to receive the first signal when the first signal is different from a second signal on the output lead and is configured to default the enable signal to suppress the first signal so as not to be received at the latch circuit when the first signal is the same as the second signal.

Abstract: Systems and methods are provided for transferring a signal from a first clock domain to a second clock domain. A system includes a pulse generator configured to receive an input data signal in the first clock domain and to generate a pulse. The system further includes an unclocked flip-flop configured to generate a first output signal. The first output signal is received by a circuit operating in the second clock domain, and the first output signal has one of a first logical value and a second logical value. The unclocked flip-flop is configured to set the first output signal to the first logical value in response to the pulse. The unclocked flip-flop is configured to reset the first output signal to the second logical value in response to a clock signal in the second clock domain and a second output signal generated by the circuit.

Abstract: Aspects of the disclosure provide a data storage circuit. The data storage circuit includes a first latch, a second latch, and a clock gating and buffer circuit. The first latch is configured to provide an intermediate output to the second latch in response to a data input when a clock signal is in a first state and to hold the intermediate output when the clock signal is in a second state, and the second latch is configured to provide a data output in response to the intermediate output and the clock signal. The clock gating and buffer circuit is configured to provide the clock signal, and to suppress providing the clock signal to one or both of the first latch and the second latch when the intermediate output stays unchanged.

Abstract: A network device includes processor devices configured to perform packet processing functions, and a shared memory system including multiple memory blocks. A memory connectivity network couples the processor devices to the shared memory system. A configuration unit configures the memory connectivity network so that processor devices are provided access to respective sets of memory blocks.

Abstract: A new simple novel Layout methodology for high integration VLSI chip is proposed, which is reduced dramatically the complexity, the cost and the schedule for implementing a complex chip such as System On a Chip (SOC) that required hierarchical layout implementation. A set of rules is provided for the place and route process.

Abstract: A new simple novel Layout methodology for high integration VLSI chip is proposed, which is reduced dramatically the complexity, the cost and the schedule for implementing a complex chip such as System On a Chip (SOC) that required hierarchical layout implementation. A set of rules is provided for the place and route process.

Abstract: A method to reduce the rate of interrupts by the central processing unit (CPU) without any loss of interrupts. The method uses two parameters. The first parameter sets the event threshold, which is the maximum value of consecutive events allowed to occur, for example, the maximum number of received data packets before an interrupt is posted (for example, a receive interrupt) to the CPU. The second parameter sets the event time-out, which is the maximum time an event can be pending before posting an interrupt to the CPU. The second parameter is needed since the flow of events in the system is unpredictable and without the time-out limit handling of the event can be delayed indefinitely.

Abstract: A method implemented by a computer network adapter for automatic retransmission of any packet involved in an unsuccessful transmission attempt due to transmit buffer underflow conditions entails the steps of (a) stopping the transmission; and (b) retrying another transmission of the packet for up to a predetermined number of attempts with an increased transmit threshold. The transmit threshold is the number of bytes of data of the packet involved in the transmission that are stored in the transmit buffer prior to start of transmission. Preferably, for the initial transmission attempt, the adapter requires only a small number of bytes of the packet to be stored in the transmit buffer. After occurrence of a buffer underflow condition, the adapter attempts a retry in accordance with the algorithm only after a substantially larger portion of the packet has entered the transmit buffer for transmission. If any retry succeeds, the adapter need not issue an interrupt.