Patents by Inventor Gil-gwang Lee

Gil-gwang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11950383
    Abstract: A display apparatus according to a concept of the disclosure includes: a display panel configured to display an image in a front direction; a top chassis positioned in a front direction of the display panel; a bottom chassis positioned in a rear direction of the display panel; a rear cover covering a rear side of the bottom chassis; and a stand member being accommodatable in the rear cover and selectively coupled with a rear surface of the rear cover, wherein the rear cover includes an accommodating portion in which the stand member is accommodated and a coupling portion coupled with the stand member, and the stand member includes an inserting protrusion which is inserted into the accommodating portion and the coupling portion.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: April 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-Bong Kim, Dong Wook Kim, Ji-Gwang Kim, Tae-Hun Kim, Yong Gu Do, Jeong Woo Park, Gil Jae Lee, Sang Young Lee, Pil Kwon Jung, Su-An Choi
  • Patent number: 7111629
    Abstract: There is provided a surface cleaning apparatus and method using plasma to remove a native oxide layer, a chemical oxide layer, and a damaged portion from a silicon substrate surface, and contaminants from a metal surface. A mixture of H2 and N2 gas is used as a first processing gas. By absorbing potential in a grounded grid or baffle between a plasma generator and a substrate, only radicals are passed to the substrate, and HF gas is used as a second processing gas. Thus a native oxide layer, a chemical oxide layer, or a damaged portion formed on the silicon substrate during etching is removed in annealing step with H2 flow. The environment of a chamber is maintained constant by introducing a conditioning gas after each wafer process. Therefore, process repeatability is improved.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: September 26, 2006
    Assignee: APL Co., Ltd.
    Inventors: Jeong-Ho Kim, Gil-Gwang Lee
  • Publication number: 20060157079
    Abstract: There is provided a surface cleaning apparatus and method using plasma to remove a native oxide layer, a chemical oxide layer, and a damaged portion from a silicon substrate surface, and contaminants from a metal surface. A mixture of H2 and N2 gas is used as a first processing gas. By absorbing potential in a grounded grid or baffle between a plasma generator and a substrate, only radicals are passed to the substrate, and HF gas is used as a second processing gas. Thus a native oxide layer, a chemical oxide layer, or a damaged portion formed on the silicon substrate during etching is removed in annealing step with H2 flow. The environment of a chamber is maintained constant by introducing a conditioning gas after each wafer process. Therefore, process repeatability is improved.
    Type: Application
    Filed: March 21, 2006
    Publication date: July 20, 2006
    Inventors: Jeong-Ho Kim, Gil-Gwang Lee
  • Patent number: 6881630
    Abstract: Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: April 19, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-sang Song, Jung-woo Park, Gil-gwang Lee, Tae-hee Choe
  • Publication number: 20050014375
    Abstract: There is provided a surface cleaning apparatus and method using plasma to remove a native oxide layer, a chemical oxide layer, and a damaged portion from a silicon substrate surface, and contaminants from a metal surface. A mixture of H2 and N2 gas is used as a first processing gas. By absorbing potential in a grounded grid or baffle between a plasma generator and a substrate, only radicals are passed to the substrate, and HF gas is used as a second processing gas. Thus a native oxide layer, a chemical oxide layer, or a damaged portion formed on the silicon substrate during etching is removed in annealing step with H2 flow. The environment of a chamber is maintained constant by introducing a conditioning gas after each wafer process. Therefore, process repeatability is improved.
    Type: Application
    Filed: May 20, 2004
    Publication date: January 20, 2005
    Inventors: Jeong-Ho Kim, Gil-Gwang Lee
  • Publication number: 20040194799
    Abstract: There is provided a surface cleaning apparatus and method using plasma to remove a native oxide layer, a chemical oxide layer, and a damaged portion from a silicon substrate surface, and contaminants from a metal surface. By absorbing potential in a grounded grid or baffle between a plasma generator and a substrate, only radicals are passed to the substrate, and HF gas is used as a second processing gas. Thus a native oxide layer, a chemical oxide layer, or a damaged portion formed on the silicon substrate during etching a contact hole is removed and the environment of a chamber is maintained constant by introducing a conditioning gas after each wafer process. Therefore, process uniformity is improved.
    Type: Application
    Filed: April 23, 2004
    Publication date: October 7, 2004
    Inventors: Jeong-Ho Kim, Gil-Gwang Lee
  • Publication number: 20030197224
    Abstract: Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure.
    Type: Application
    Filed: April 30, 2003
    Publication date: October 23, 2003
    Inventors: Won-sang Song, Jung-woo Park, Gil-gwang Lee, Tae-hee Choe
  • Patent number: 6580134
    Abstract: Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: June 17, 2003
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Won-sang Song, Jung-woo Park, Gil-gwang Lee, Tae-hee Choe
  • Publication number: 20020124867
    Abstract: There is provided a surface cleaning apparatus and method using plasma to remove a native oxide layer, a chemical oxide layer, and a damaged portion from a silicon substrate surface, and contaminants from a metal surface. By absorbing potential in a grounded grid or baffle between a plasma generator and a substrate, only radicals are passed to the substrate, and HF gas is used as a second processing gas. Thus a native oxide layer, a chemical oxide layer, or a damaged portion formed on the silicon substrate during etching a contact hole is removed and the environment of a chamber is maintained constant by introducing a conditioning gas after each wafer process. Therefore, process uniformity is improved.
    Type: Application
    Filed: January 4, 2002
    Publication date: September 12, 2002
    Applicant: APL CO., LTD.
    Inventors: Jeong-Ho Kim, Gil-Gwang Lee
  • Patent number: 5624498
    Abstract: A gas supply apparatus, for use in a semiconductor device manufacturing process, provides a showerhead for evenly supplying various kinds of gases to a reaction chamber. The gas supplying apparatus for use in the formation of a thin film of a semiconductor device includes a first porous plate having a plurality of first holes formed throughout its surface, and a central bore formed at its center; and a second porous plate having first projections which are regularly formed throughout its central portion, and second projections which contain depressions continuously formed around the first projections. The gas supplying apparatus evenly distributes gas into the reaction chamber, thereby improving the uniformity of the film thickness to be grown on a substrate.
    Type: Grant
    Filed: December 8, 1994
    Date of Patent: April 29, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gil-Gwang Lee, Kazuyuki Fujihara, Kyu-hwan Chang