Patents by Inventor Gil Huang

Gil Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7459386
    Abstract: A method for forming solder bumps (or solder balls after reflow) of improved height and reliability is provided. In one embodiment, a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad is provided. A layer of under bump metal (UBM) is formed above the passivation layer and the contact pad. A first patterned and etched photoresist layer is provided above the UBM layer, the first patterned and etched photoresist layer defining at least one first opening therein. A second patterned and etched photoresist layer is provided above the first patterned and etched photoresist layer, the second patterned and etched photoresist layer defining at least one second opening therein, the second opening being wider than the first opening. A solder material is filled in the at least one first opening and substantially filled in the at least one second opening.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: December 2, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hsin Tseng, Gil Huang, Huei-Mei Yu, Chia-Jen Cheng, Ken Sun, Chien-Tung Yu, Blenny Chang, Chih Yang Chan, Jian-Wen Luo, Owen Chen
  • Patent number: 7456090
    Abstract: A method of manufacturing a solder bump structure on a semiconductor device is provided. In one embodiment, a semiconductor substrate is provided having a bonding pad and a passivation layer formed thereabove, the passivation layer having an opening therein exposing a portion of the bonding pad. A first under bump metallization (UBM) layer is formed over the bonding pad and the passivation layer. A mask layer is placed over the first UBM layer, the mask layer having an opening therein exposing a portion of the first UBM layer. The mask layer is thereafter etched to create a recess at the edges between the first UBM layer and the mask layer. A second UBM layer is deposited in the opening of the mask layer, the second UBM layer filling the recess and a portion of the opening of the mask layer.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: November 25, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Blenny Chang, Hsiu-Mei Yu, Gil Huang, Sung-Cheng Chiu
  • Publication number: 20080157362
    Abstract: A method of manufacturing a solder bump structure on a semiconductor device is provided. In one embodiment, a semiconductor substrate is provided having a bonding pad and a passivation layer formed thereabove, the passivation layer having an opening therein exposing a portion of the bonding pad. A first under bump metallization (UBM) layer is formed over the bonding pad and the passivation layer. A mask layer is placed over the first UBM layer, the mask layer having an opening therein exposing a portion of the first UBM layer. The mask layer is thereafter etched to create a recess at the edges between the first UBM layer and the mask layer. A second UBM layer is deposited in the opening of the mask layer, the second UBM layer filling the recess and a portion of the opening of the mask layer.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Blenny Chang, Hsiu-Mei Yu, Gil Huang, Sung-Cheng Chiu
  • Patent number: 7378724
    Abstract: A method for providing a cavity structure on a semiconductor device is provided. The method of forming the cavity structure, which may be particularly useful in packaging an image sensor, includes forming a spacer layer over a substrate. The spacer layer may be formed from a photo-sensitive material which may be patterned using photolithography techniques to form cavity walls surrounding dies on the wafer. A packaging layer, such as a substantially transparent layer, may be placed directly upon the cavity walls prior to curing. In another embodiment, the cavity walls are cured, an adhesive is applied to a surface of the cavity walls, and the packaging layer placed upon the adhesive. Thereafter, the wafer may be diced and the individual dies may be packaged for use.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: May 27, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Mei Yu, Gil Huang, Chien-Tung Yu, Owen Chen
  • Publication number: 20060213804
    Abstract: A method for providing a cavity structure on a semiconductor device is provided. The method of forming the cavity structure, which may be particularly useful in packaging an image sensor, includes forming a spacer layer over a substrate. The spacer layer may be formed from a photo-sensitive material which may be patterned using photolithography techniques to form cavity walls surrounding dies on the wafer. A packaging layer, such as a substantially transparent layer, may be placed directly upon the cavity walls prior to curing. In another embodiment, the cavity walls are cured, an adhesive is applied to a surface of the cavity walls, and the packaging layer placed upon the adhesive. Thereafter, the wafer may be diced and the individual dies may be packaged for use.
    Type: Application
    Filed: June 24, 2005
    Publication date: September 28, 2006
    Inventors: Hsiu-Mei Yu, Gil Huang, Chien-Tung Yu, Owen Chen
  • Publication number: 20060105560
    Abstract: A method for forming solder bumps (or solder balls after reflow) of improved height and reliability is provided. In one embodiment, a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad is provided. A layer of under bump metal (UBM) is formed above the passivation layer and the contact pad. A first patterned and etched photoresist layer is provided above the UBM layer, the first patterned and etched photoresist layer defining at least one first opening therein. A second patterned and etched photoresist layer is provided above the first patterned and etched photoresist layer, the second patterned and etched photoresist layer defining at least one second opening therein, the second opening being wider than the first opening. A solder material is filled in the at least one first opening and substantially filled in the at least one second opening.
    Type: Application
    Filed: November 16, 2004
    Publication date: May 18, 2006
    Inventors: Li-Hsin Tseng, Gil Huang, Huei-Mei Yu, Chia-Jen Cheng, Ken Sun, Chien-Tung Yu, Blenny Chang, Chih Chan, Jian-Wen Luo, Owen Chen