Patents by Inventor Gil Israel Dogon
Gil Israel Dogon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220276964Abstract: A multi-core processor configured to improve processing performance in certain computing contexts is provided. The multi-core processor includes multiple processing cores that implement barrel threading to execute multiple instruction threads in parallel while ensuring that the effects of an idle instruction or thread upon the performance of the processor is minimized. The multiple cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate inter-cache coherency issues. The barrel-threading can minimize the latency impacts associated with a shared data cache. In some examples, the multi-core processor can also include a serial processor configured to execute single threaded programming code that may not yield satisfactory performance in a processing environment that employs barrel threading.Type: ApplicationFiled: February 15, 2022Publication date: September 1, 2022Inventors: Yosef Kreinin, Yosi Arbeli, Gil Israel Dogon
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Patent number: 11294815Abstract: A multi-core processor configured to improve processing performance in certain computing contexts is provided. The multi-core processor includes multiple processing cores that implement barrel threading to execute multiple instruction threads in parallel while ensuring that the effects of an idle instruction or thread upon the performance of the processor is minimized. The multiple cores can also share a common data cache, thereby minimizing the need for expensive and complex mechanisms to mitigate inter-cache coherency issues. The barrel-threading can minimize the latency impacts associated with a shared data cache. In some examples, the multi-core processor can also include a serial processor configured to execute single threaded programming code that may not yield satisfactory performance in a processing environment that employs barrel threading.Type: GrantFiled: June 9, 2016Date of Patent: April 5, 2022Assignee: Mobileye Vision Technologies Ltd.Inventors: Yosef Kreinin, Yosi Arbeli, Gil Israel Dogon
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Publication number: 20220070116Abstract: There may be provided a non-uniform Benes network, that may include a first Benes network portion that has a first number (k) of first inputs and k first outputs; a second Benes network portion that has a second number (j) of second inputs and j second outputs; wherein j is smaller than k; and a set of multiplexers that are coupled between a set of switches of an intermediate layer of the first Benes network portion and a first layer of the second Benes network layer.Type: ApplicationFiled: November 11, 2021Publication date: March 3, 2022Inventors: Daniel SREBNIK, Emmanuel Sixou, Gil Israel Dogon, Dror Livne
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Patent number: 11178072Abstract: There may be provided a non-uniform Benes network, that may include a first Benes network portion that has a first number (k) of first inputs and k first outputs; a second Benes network portion that has a second number (j) of second inputs and j second outputs; wherein j is smaller than k; and a set of multiplexers that are coupled between a set of switches of an intermediate layer of the first Benes network portion and a first layer of the second Benes network layer.Type: GrantFiled: December 14, 2017Date of Patent: November 16, 2021Assignee: Mobileye Vision Technologies Ltd.Inventors: Daniel Srebnik, Emmanuel Sixou, Gil Israel Dogon, Dror Livne
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Publication number: 20200319891Abstract: An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K? bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J? bits per word, wherein J? is less than N multiplied by K?.Type: ApplicationFiled: June 24, 2020Publication date: October 8, 2020Inventors: Gil Israel Dogon, Yosi Arbeli, Yosef Kreinin
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Patent number: 10698694Abstract: An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K? bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J? bits per word, wherein J? is less than N multiplied by K?.Type: GrantFiled: January 31, 2019Date of Patent: June 30, 2020Assignee: Mobileye Vision Technologies Ltd.Inventors: Gil Israel Dogon, Yosi Arbeli, Yosef Kreinin
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Patent number: 10318308Abstract: An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K? bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J? bits per lane, wherein J? is less than N multiplied by K?.Type: GrantFiled: October 31, 2012Date of Patent: June 11, 2019Assignee: Mobileye Vision Technologies Ltd.Inventors: Gil Israel Dogon, Yosi Arbeli, Yosef Kreinin
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Publication number: 20190163495Abstract: An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K? bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J? bits per word, wherein J? is less than N multiplied by K?.Type: ApplicationFiled: January 31, 2019Publication date: May 30, 2019Inventors: Gil Israel Dogon, Yosi Arbeli, Yosef Kreinin
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Patent number: 10255232Abstract: A processor with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking pipelined execution of the processor.Type: GrantFiled: October 6, 2017Date of Patent: April 9, 2019Assignee: MOBILEYE VISION TECHNOLOGIES LTD.Inventors: Gil Israel Dogon, Yosi Arbeli, Yosef Kreinin
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Publication number: 20190065385Abstract: A method of calculating warp results, the method may include executing, for each target pixel out of a group of target pixels, a warp calculation process that comprises: receiving, by a first group of processing units of an array of processing units, a first weight and a second weight associated with the target pixel; receiving, by a second group of processing units of the array, values of neighboring source pixels associated with the target pixel; calculating, by the second group, a warp result based on in response to values of the neighboring source pixels and the pair of weights; and providing the warp result to a memory module.Type: ApplicationFiled: September 24, 2018Publication date: February 28, 2019Inventors: Daniel Srebnik, Emmanuel Sixou, Gil Israel Dogon
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Patent number: 10157138Abstract: A method of calculating warp results for at least one out of driver assistance and autonomous driving, the method may include executing, for each target pixel out of a group of target pixels, a warp calculation process that includes: (a) Receiving, by a first group of processing units of an array of processing units, a first weight and a second weight associated with the target pixel. (b) Receiving, by a second group of processing units of the array, values of neighboring source pixels associated with the target pixel (c) Calculating, by the second group, a warp result based on in response to values of the neighboring source pixels and the pair of weights (d) And providing the warp result to a memory module.Type: GrantFiled: June 9, 2016Date of Patent: December 18, 2018Assignee: MOBILEYE VISION TECHNOLOGIES LTD.Inventors: Daniel Srebnik, Emmanuel Sixou, Gil Israel Dogon
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Publication number: 20180176151Abstract: There may be provided a non-uniform Benes network, that may include a first Benes network portion that has a first number (k) of first inputs and k first outputs; a second Benes network portion that has a second number (j) of second inputs and j second outputs; wherein j is smaller than k; and a set of multiplexers that are coupled between a set of switches of an intermediate layer of the first Benes network portion and a first layer of the second Benes network layer.Type: ApplicationFiled: December 14, 2017Publication date: June 21, 2018Inventors: Daniel Srebnik, Emmanuel Sixou, Gil Israel Dogon, Dror Livneh
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Publication number: 20180095934Abstract: A processor with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking pipelined execution of the processor.Type: ApplicationFiled: October 6, 2017Publication date: April 5, 2018Inventors: Gil Israel Dogon, Yosi Arbeli, Yosef Kreinin
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Patent number: 9785609Abstract: A processor with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking pipelined execution of the processor.Type: GrantFiled: January 21, 2016Date of Patent: October 10, 2017Assignee: Mobileye Vision Technologies Ltd.Inventors: Gil Israel Dogon, Yosi Arbeli, Yosef Kreinin
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Publication number: 20160364835Abstract: A method of calculating warp results, the method may include executing, for each target pixel out of a group of target pixels, a warp calculation process that comprises: receiving, by a first group of processing units of an array of processing units, a first weight and a second weight associated with the target pixel; receiving, by a second group of processing units of the array, values of neighboring source pixels associated with the target pixel; calculating, by the second group, a warp result based on in response to values of the neighboring source pixels and the pair of weights; and providing the warp result to a memory module.Type: ApplicationFiled: June 9, 2016Publication date: December 15, 2016Inventors: Daniel Srebnik, Emmanuel Sixou, Gil Israel Dogon
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Publication number: 20160140080Abstract: A processor with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking pipelined execution of the processor.Type: ApplicationFiled: January 21, 2016Publication date: May 19, 2016Applicant: Mobileye Vision Technologies Ltd.Inventors: Gil Israel Dogon, Yosi Arbeli, Yosef Kreinin
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Patent number: 9256480Abstract: A processor with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking pipelined execution of the processor.Type: GrantFiled: July 25, 2012Date of Patent: February 9, 2016Assignee: MOBILEYE VISION TECHNOLOGIES LTD.Inventors: Gil Israel Dogon, Yosi Arbeli, Yosef Kreinin
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Publication number: 20140122551Abstract: An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K? bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J? bits per word, wherein J? is less than N multiplied by K?.Type: ApplicationFiled: October 31, 2012Publication date: May 1, 2014Applicant: MOBILEYE TECHNOLOGIES LIMITEDInventors: Gil Israel Dogon, Yosi Arbeli, Yosef Kreinin
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Publication number: 20140033203Abstract: A processor with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking pipelined execution of the processor.Type: ApplicationFiled: July 25, 2012Publication date: January 30, 2014Inventors: Gil Israel Dogon, Yosi Arbeli, Yosef Kreinin