Patents by Inventor Gil Stoler
Gil Stoler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8688911Abstract: Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core including a core bus agent, a bus interface unit (BIU), and a bridge module operatively coupling the processing core to the BIU, the bridge module configured to selectively route information from the core bus agent to a cache or to the BIU by bypassing the cache. Other embodiments are also described and claimed.Type: GrantFiled: November 23, 2009Date of Patent: April 1, 2014Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Tarek Rohana, Gil Stoler
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Patent number: 8499123Abstract: Embodiments of the present disclosure provide a command processing pipeline operatively coupled to an N-way cache and configured to process a sequence of cache commands. A way of the N ways of the cache with which an address of a cache command matches is a hit way for the cache command in case the cache command is a hit. In one embodiment, the command processing pipeline may be configured to receive a first cache command from one of the plurality of processing cores, select a way, from the N ways, as a potential eviction way, and generate, based at least in part on the received first cache command, N selection signals corresponding to the N ways, wherein each selection signal is indicative of whether the corresponding way is (A). the hit way and/or the eviction way, or (B). neither the hit way nor the eviction way.Type: GrantFiled: January 25, 2012Date of Patent: July 30, 2013Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Tarek Rohana, Gil Stoler
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Patent number: 8484421Abstract: Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core, and a cache including a cache instruction port, a cache data port, and a port utilization circuitry configured to selectively fetch instructions through the cache instruction port and selectively pre-fetch instructions through the cache data port. Other embodiments are also described and claimed.Type: GrantFiled: November 23, 2009Date of Patent: July 9, 2013Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Tarek Rohana, Adi Habusha, Gil Stoler
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Patent number: 8332590Abstract: A command processing pipeline is coupled to a shared cache. The command processing pipeline comprises (i) a first command processing stage configured to sequentially receive and process first and second cache commands, and (ii) a second command processing stage coupled to the first command processing stage. The first and the second command processing stages are two consecutive command processing stages of the command processing pipeline. The first and second command processing stages may access different groups of cache resources, and the first and second cache commands may be processed during consecutive clock cycles of a clock signal. Processing of the second cache command may be performed independently of an outcome of processing the first cache command by the first command processing stage. A third command processing stage may write data associated with the first cache command to one of a valid memory and a data memory included in the cache.Type: GrantFiled: June 24, 2009Date of Patent: December 11, 2012Assignee: Marvell Israel (M.I.S.L.) Ltd.Inventors: Tarek Rohana, Gil Stoler
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Patent number: 8117395Abstract: Some of the embodiments of the present disclosure provide a command processing pipeline to be operatively coupled to a shared cache, the command processing pipeline comprising a command processing pipeline operatively coupled to the N-way cache and configured to process a sequence of cache commands, wherein a way of the N ways of the cache with which an address of a cache command matches is a hit way for the cache command in case the cache command is a hit. In one embodiment, the command processing pipeline may be configured to receive a first cache command from one of the plurality of processing cores, select a way, from the N ways, as a potential eviction way, and generate, based at least in part on the received first cache command, N selection signals corresponding to the N ways, wherein each selection signal is indicative of whether the corresponding way is (A). the hit way and/or the eviction way, or (B). neither the hit way nor the eviction way. Other embodiments are also described and claimed.Type: GrantFiled: July 21, 2009Date of Patent: February 14, 2012Assignee: Marvell Israel (MISL) Ltd.Inventors: Tarek Rohana, Gil Stoler
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Patent number: 8089378Abstract: Some of the embodiments of the present disclosure provide a method of transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the method comprising receiving first fast data from the fast clock domain during a first fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; and propagating, during the first full fast clock cycle in the first slow clock cycle, the received first fast data to the slow clock domain. Other embodiments are also described and claimed.Type: GrantFiled: February 16, 2010Date of Patent: January 3, 2012Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Gil Stoler, Eitan Joshua, Shaul Chapman
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Patent number: 7932768Abstract: An apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.Type: GrantFiled: December 30, 2009Date of Patent: April 26, 2011Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Ido Bourstein, Yiftach Banai, Gil Stoler
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Publication number: 20100102869Abstract: An apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.Type: ApplicationFiled: December 30, 2009Publication date: April 29, 2010Inventors: Gil Stoler, Ido Bourstein, Yiftach Banai
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Patent number: 7652516Abstract: A apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.Type: GrantFiled: October 22, 2007Date of Patent: January 26, 2010Assignee: Marvell Israel (M.I.S.L.) Ltd.Inventors: Ido Bourstein, Yiftach Banai, Gil Stoler
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Publication number: 20080094117Abstract: A apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.Type: ApplicationFiled: October 22, 2007Publication date: April 24, 2008Inventors: Gil Stoler, Ido Bourstein, Yiftach Banai
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Patent number: 7245627Abstract: A network interface device includes a fabric interface, adapted to exchange messages over a switch fabric with a plurality of host processors, the messages containing data, and a network interface, including one or more ports adapted to be coupled to a network external to the switch fabric. Message processing circuitry is coupled between the fabric interface and the network interface, so as to enable at least first and second host processors among the plurality of the host processors to use a single one of the ports substantially simultaneously so as to transmit and receive frames containing the data over the network.Type: GrantFiled: April 23, 2002Date of Patent: July 17, 2007Assignee: Mellanox Technologies Ltd.Inventors: Dror Goldenberg, Gil Bloch, Gil Stoler, Diego Crupnicoff, Michael Kagan
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Patent number: 7224669Abstract: A method for static rate flow control includes receiving a sequence of data packets for transmission over a network, including at least first and second packets having a common destination address on the network, the first and second packets having respective first and second lengths, and transmitting the first packet to the destination address. Responsive to transmitting the first packet, an entry is placed in a flow control table, and a timeout period is set for the entry responsive to the first length. The second packet is transmitted only after the timeout period has expired.Type: GrantFiled: January 22, 2002Date of Patent: May 29, 2007Assignee: Mellandx Technologies Ltd.Inventors: Michael Kagan, Diego Crupnicoff, Ariel Shachar, Gil Stoler, Roi Rahamim
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Patent number: 7149227Abstract: A method for allocating a processing resource among multiple inputs includes defining a sequence of multiplexing iterations, each such iteration including a first plurality of windows, each such window containing a second plurality of time slots. A respective weight is assigned to each of the inputs, and each of the inputs is allotted one of the time slots in each of a respective number of the windows in each of the iterations, the respective number being determined by the respective weight. Each of the inputs is then provided with access to the processing resource during the time slots allotted thereto.Type: GrantFiled: May 31, 2002Date of Patent: December 12, 2006Assignee: Mellanox Technologies Ltd.Inventors: Gil Stoler, Diego Crupnicoff
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Publication number: 20040218623Abstract: A network interface adapter includes a memory interface, for coupling to a memory containing a first data packet composed in accordance with a first communication protocol, and a network interface, for coupling to a packet communication network. Packet processing circuitry in the adapter reads the first data packet from the memory via the memory interface, computes a checksum of the first data packet, inserts the checksum in the first data packet in accordance with the first communication protocol, and encapsulates the first data packet in a payload of a second data packet in accordance with a second communication protocol applicable to the packet communication network, so as to transmit the second data packet over the network via the network interface. The circuitry likewise computes checksums of incoming encapsulated data packets from the network.Type: ApplicationFiled: May 1, 2003Publication date: November 4, 2004Inventors: Dror Goldenberg, Michael Kagan, Benny Koren, Gil Stoler, Peter Paneah, Roi Rachamim, Gilad Shainer, Rony Gutierrez, Sagi Rotem, Dror Bohrer
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Publication number: 20030223453Abstract: A method for allocating a processing resource among multiple inputs includes defining a sequence of multiplexing iterations, each such iteration including a first plurality of windows, each such window containing a second plurality of time slots. A respective weight is assigned to each of the inputs, and each of the inputs is allotted one of the time slots in each of a respective number of the windows in each of the iterations, the respective number being determined by the respective weight. Each of the inputs is then provided with access to the processing resource during the time slots allotted thereto.Type: ApplicationFiled: May 31, 2002Publication date: December 4, 2003Inventors: Gil Stoler, Diego Crupnicoff
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Publication number: 20030200315Abstract: A network interface device includes a fabric interface, adapted to exchange messages over a switch fabric with a plurality of host processors, the messages containing data, and a network interface, including one or more ports adapted to be coupled to a network external to the switch fabric. Message processing circuitry is coupled between the fabric interface and the network interface, so as to enable at least first and second host processors among the plurality of the host processors to use a single one of the ports substantially simultaneously so as to transmit and receive frames containing the data over the network.Type: ApplicationFiled: April 23, 2002Publication date: October 23, 2003Applicant: MELLANOX TECHNOLOGIES LTD.Inventors: Dror Goldenberg, Gil Bloch, Gil Stoler, Diego Crupnicoff, Michael Kagan
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Publication number: 20030137935Abstract: A method for static rate flow control includes receiving a sequence of data packets for transmission over a network, including at least first and second packets having a common destination address on the network, the first and second packets having respective first and second lengths, and transmitting the first packet to the destination address. Responsive to transmitting the first packet, an entry is placed in a flow control table, and a timeout period is set for the entry responsive to the first length. The second packet is transmitted only after the timeout period has expired.Type: ApplicationFiled: January 22, 2002Publication date: July 24, 2003Inventors: Michael Kagan, Diego Crupnicoff, Ariel Shachar, Gil Stoler, Roi Rahamim
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Patent number: 6016551Abstract: A microprocessor having a cache memory unit, an execution unit, and clock masking circuitry is described. Both units are responsive to a clock signal that can be masked by the clock masking circuitry in order to reduce the power consumption of the microprocessor. Based on a signal that indicates a potential impending cache snoop, the clock masking circuitry can unmask the clock signal to the cache unit without unmasking the clock signal to the execution unit.Type: GrantFiled: December 19, 1997Date of Patent: January 18, 2000Assignee: Intel CorporationInventors: Gil Stoler, Tosaki Nakanishi
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Patent number: 5764932Abstract: To improve computer performance, a second processor can be added to a computer system. However, when a second processor is added to a computer system, a dual processing protocol is required to ensure that the two processors share the computer resources. A robust dual processing protocol is introduced that allows two processors to share a single processor bus in an efficient manner. The dual processing protocol allows pipelined bus transfers wherein partial control of the bus is transferred. Furthermore, the dual processing protocol ensures cache coherency by having any modified cache line written back to main memory when a memory location represent by a modified internal cache line is accessed. The dual processing Protocol is designed to support a well defined fair and robust arbitration DP protocol between two processors that is independent of the core frequency and the bus fraction ratio.Type: GrantFiled: December 23, 1996Date of Patent: June 9, 1998Assignee: Intel CorporationInventors: Simcha Gochman, Gil Stoler