Abstract: An integrated packet switching and circuit switching system comprising a number of switching modules each connected to a corresponding plurality of user terminals. Each switching module includes a time-slot interchange unit for providing circuit-switched communication channels and a control unit that controls the operation of the time-slot interchange unit. Each switching module also includes a packet switching unit used both to provide packet-switched communication channels among the user terminals connected to that switching module, and to switch control information between the user terminals and the control unit to establish circuit-switched calls and packet-switched calls. A time-multiplexed switch interconnects the switching modules to provide circuit-switched communication channels and packet-switched communication channels between user terminals of different switching modules.

Abstract: An integrated packet switching and circuit switching system comprising a number of switching modules each connected to a different plurality of user terminals. Each switching module includes a time-slot interchange unit for providing circuit-switched communication channels and a control unit that controls the operation of the time-slot interchange unit. Each switching module also includes a packet switching unit used both to provide packet-switched communication channels among the user terminals connected to that switching module, and to switch control information between the user terminals and the control unit to establish circuit-switched calls and packet-switched calls.

Abstract: Each power diode in an ORed direct-current power distribution system has connected thereacross, between the respective load and source terminals of the power diode, a series connection of respective first and second light-emitting diodes (LEDs) with the LEDs being similarly poled with respect to their common connection, with the power diode and the first LED being oppositely poled with respect to the power diode load terminal, with a resistance connected between the common LED connection and the power supply return. A resistance-LED arrangement is also provided in parallel with each nonindicating fuse. The ON (fully conducting--showing detectable visible light) and OFF (not fully conducting--not showing detectable visible light) patterns of the LEDs, both under the condition of normal voltage on each power bus and under the condition where the relative voltage between buses is varied slightly, can be used for circuit failure diagnostics.

Abstract: A circuit for combining a plurality of delta modulated speech signals, each signal being represented by a stream of input bits. Once each clock cycle, a multiplexer (101) sequentially applies one bit from each of the streams to an up-down counter (103) to either increment or decrement a count contained therein. The state of the most significant bit position of the up-down counter is then stored in a D-type flip-flop (104). A feedback bit assumes the inverse state of the stored most significant bit position and is sequentially applied under the control of a binary counter (102) to the up-down counter along with a bit from each of the streams during the next clock cycle. An output bit assumes the state of the stored most significant bit position, and an output signal consisting of a plurality of output bits from successive clock cycles represents the approximate linear sum of the delta modulated speech signals.