Patents by Inventor Gilbert M. Wolrich

Gilbert M. Wolrich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9900770
    Abstract: Vector instructions for performing SNOW 3G wireless security operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first operand of the first instruction specifying a first vector register that stores a current state of a finite state machine (FSM). The execution circuitry also receives a second operand of the first instruction specifying a second vector register that stores data elements of a liner feedback shift register (LFSR) that are needed for updating the FSM. The execution circuitry executes the first instruction to produce a updated state of the FSM and an output of the FSM in a destination operand of the first instruction.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: February 20, 2018
    Assignee: Intel Corporation
    Inventors: Gilbert M. Wolrich, Vinodh Gopal, Erdinc Ozturk, Kirk S. Yap, Wajdi K. Feghali
  • Patent number: 9898300
    Abstract: Vector instructions for performing ZUC stream cipher operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first vector instruction to perform an update to a liner feedback shift register (LFSR), and receives a second vector instruction to perform an update to a state of a finite state machine (FSM), where the FSM receives inputs from re-ordered bits of the LFSR. The execution circuitry executes the first vector instruction and the second vector instruction in a single-instruction multiple data (SIMD) pipeline.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: February 20, 2018
    Assignee: Intel Corporation
    Inventors: Gilbert M. Wolrich, Vinodh Gopal, Kirk S. Yap, Wajdi K. Feghali
  • Patent number: 9871535
    Abstract: A processing device includes an accelerator circuit to identify a byte in a byte stream, determine whether a first byte string starting from a first byte position of the byte matches a second byte string starting from a second byte position, responsive to determining that the first byte string matches the second byte string, generate a token comprising a first symbol encoding a length of the first byte string and a second symbol encoding a byte distance between the first byte position and the second byte position, and responsive to determining that the first byte string does not match another byte string, generate the token comprising the first symbol comprising the byte and a second symbol encoding a determined value.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 16, 2018
    Assignee: Intel Corporation
    Inventors: James D. Guilford, Vinodh Gopal, Gilbert M. Wolrich, Daniel F. Cutter
  • Publication number: 20180011656
    Abstract: A processing system is provided that includes a memory for storing an input bit stream and a processing logic, operatively coupled to the memory, to generate a first score based on: a first set of matching data related to a match between a first bit subsequence and a candidate bit subsequence within the input bit stream, and a first distance of the candidate bit subsequence from the first set of matching data. A second score is generated based on a second set of matching data related to a match between a second bit subsequence and the candidate bit subsequence, and a second distance of the candidate bit subsequence from the second set of matching data. A code to replace the first or second bit subsequence in an output bit stream is identified. Selection of the one of the bit subsequences to replace is based on a comparison of the scores.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 11, 2018
    Inventors: James D. Guilford, Vinodh Gopal, Gilbert M. Wolrich, Daniel F. Cutter
  • Publication number: 20170351519
    Abstract: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.
    Type: Application
    Filed: August 25, 2017
    Publication date: December 7, 2017
    Applicant: lntel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Erdinc Ozturk, Wajdi K. Feghali, Gilbert M. Wolrich, Martin G. Dixon
  • Patent number: 9772845
    Abstract: A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: September 26, 2017
    Assignee: Intel Corporation
    Inventors: Kirk S. Yap, Gilbert M. Wolrich, James D. Guilford, Vinodh Gopal, Erdinc Ozturk, Sean M. Gulley, Wajdi K. Feghali, Martin G. Dixon
  • Publication number: 20170272096
    Abstract: Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. For example, in embodiment a hardware apparatus comprises an input buffer to store incoming data from a compressed stream, a selector to select at least one byte stored in the input buffer, a decoder to decode the selected at least one byte and determine if the decoded at least one byte is a literal or a symbol, an overlap condition, a size of a record from the decoded stream, a length value of the data to be retrieved from the decoded stream, and an offset value for the decoded data, and a token format converter to convert the decoded data and data from source and destination offset base registers into a fixed-length token.
    Type: Application
    Filed: April 4, 2017
    Publication date: September 21, 2017
    Inventors: VINODH GOPAL, JAMES D. GUILFORD, KIRK S. YAP, SEAN M. GULLEY, GILBERT M. WOLRICH
  • Patent number: 9768802
    Abstract: Example data compression methods disclosed herein include determining a first hash chain index corresponding to a first position in an input data buffer based on a first group of bytes accessed from the input data buffer beginning at a first look-ahead offset from the first position. If a first hash chain (indexed by the first hash chain index), does not satisfy a quality condition, a second hash chain index corresponding to the first position in the input data buffer based on a second group of bytes accessed from the input data buffer beginning at a second look-ahead offset from the first position is determined. The input data buffer is searched at respective adjusted buffer positions to find a second string of data bytes matching a first string of data bytes and information related to the second string of data bytes is provided to an encoder to output compressed data.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Daniel F. Cutter
  • Publication number: 20170255469
    Abstract: Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3 message expansions, from the first and second source data operand sets, determined by the specified expansion extent and store the result into a SIMD destination register. Some embodiments also execute instructions for a SIMD SM3 hash round-slice portion of the hashing algorithm, from an intermediate hash value input, a source data set, and a round constant set. Processor execution units perform a set of SM3 hashing round iterations upon the source data set, applying the intermediate hash value input and the round constant set, and store a new hash value result in a SIMD destination register.
    Type: Application
    Filed: May 19, 2017
    Publication date: September 7, 2017
    Applicant: lntel Corporation
    Inventors: Gilbert M. Wolrich, Vinodh Gopal, Sean M. Gulley, Kirk S. Yap, Wajdi K. Feghali
  • Patent number: 9747105
    Abstract: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: August 29, 2017
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Erdine Ozturk, Wajdi K. Feghali, Gilbert M. Wolrich, Martin G. Dixon
  • Patent number: 9740484
    Abstract: An apparatus and method are described for processing bit streams using bit-oriented instructions. For example, a method according to one embodiment includes the operations of: executing an instruction to get bits for an operation, the instruction identifying a start bit address and a number of bits to be retrieved; retrieving the bits identified by the start bit address and number of bits from a bit-oriented register or cache; and performing a sequence of specified bit operations on the retrieved bits to generate results.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 22, 2017
    Assignee: INTEL CORPORATION
    Inventors: Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Erdinc Ozturk, Wajdi K. Feghali, Kirk S. Yap, Sean M. Gulley, Martin G. Dixon, Robert S. Chappell
  • Publication number: 20170235571
    Abstract: According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.
    Type: Application
    Filed: January 3, 2017
    Publication date: August 17, 2017
    Inventors: Vinodh Gopal, Erdinc Ozturk, James D. Guilford, Gilbert M. Wolrich
  • Patent number: 9733858
    Abstract: A processing system is provided that includes a memory for storing an input bit stream and a processing logic, operatively coupled to the memory, to generate a first score based on: a first set of matching data related to a match between a first bit subsequence and a candidate bit subsequence within the input bit stream, and a first distance of the candidate bit subsequence from the first set of matching data. A second score is generated based on a second set of matching data related to a match between a second bit subsequence and the candidate bit subsequence, and a second distance of the candidate bit subsequence from the second set of matching data. A code to replace the first or second bit subsequence in an output bit stream is identified. Selection of the one of the bit subsequences to replace is based on a comparison of the scores.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: James D. Guilford, Vinodh Gopal, Gilbert M. Wolrich, Daniel F. Cutter
  • Patent number: 9690488
    Abstract: In an embodiment, a processor includes hardware processing cores, a cache memory, and a compression accelerator comprising a hash table memory. The compression accelerator is to: determine a hash value for input data to be compressed; read a first plurality of N location values stored in a hash table entry indexed by the hash value; perform a first set of string searches in parallel from a history buffer using the first plurality of N location values stored in the hash table entry; read a second plurality of N location values stored in a first overflow table entry indexed by a first overflow pointer included in the hash table entry; and perform a second set of string searches in parallel from the history buffer using the second plurality of N location values stored in the first overflow table entry. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Daniel F. Cutter
  • Publication number: 20170177404
    Abstract: Methods and apparatuses relating to stateful compression and decompression operations are described. In one embodiment, hardware processor includes a core to execute a thread and offload at least one of a compression and decompression thread, and a hardware compression and decompression accelerator to execute the at least one of the compression and decompression thread to consume input and generate output data, wherein the hardware compression and decompression accelerator is coupled to a plurality of input buffers to store the input data, a plurality of output buffers to store the output data, an input buffer descriptor array with an entry for each respective input buffer, an input buffer response descriptor array with a corresponding response entry for each respective input buffer, an output buffer descriptor array with an entry for each respective output buffer, and an output buffer response descriptor array with a corresponding response entry for each respective output buffer.
    Type: Application
    Filed: December 20, 2015
    Publication date: June 22, 2017
    Inventors: Tracy G. Drysdale, James D. Guilford, Vinodh Gopal, Gilbert M. Wolrich, James T. Kukunas
  • Publication number: 20170147255
    Abstract: A processing system is provided that includes a memory for storing an input bit stream and a processing logic, operatively coupled to the memory, to generate a first score based on: a first set of matching data related to a match between a first bit subsequence and a candidate bit subsequence within the input bit stream, and a first distance of the candidate bit subsequence from the first set of matching data. A second score is generated based on a second set of matching data related to a match between a second bit subsequence and the candidate bit subsequence, and a second distance of the candidate bit subsequence from the second set of matching data. A code to replace the first or second bit subsequence in an output bit stream is identified. Selection of the one of the bit subsequences to replace is based on a comparison of the scores.
    Type: Application
    Filed: February 8, 2017
    Publication date: May 25, 2017
    Inventors: James D. Guilford, Vinodh Gopal, Gilbert M. Wolrich, Daniel F. Cutter
  • Publication number: 20170147341
    Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
    Type: Application
    Filed: December 31, 2016
    Publication date: May 25, 2017
    Inventors: Kirk S. YAP, Gilbert M. WOLRICH, James D. GUILFORD, Vinodh GOPAL, Erdinc OZTURK, Sean M. GULLEY, Wajdi K. FEGHALI, Martin G. DIXON
  • Publication number: 20170147348
    Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
    Type: Application
    Filed: December 31, 2016
    Publication date: May 25, 2017
    Inventors: Kirk S. YAP, Gilbert M. WOLRICH, James D. GUILFORD, Vinodh GOPAL, Erdinc OZTURK, Sean M. GULLEY, Wajdi K. FEGHALI, Martin G. DIXON
  • Publication number: 20170147343
    Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
    Type: Application
    Filed: December 31, 2016
    Publication date: May 25, 2017
    Inventors: Kirk S. YAP, Gilbert M. WOLRICH, James D. GUILFORD, Vinodh GOPAL, Erdinc OZTURK, Sean M. GULLEY, Wajdi K. FEGHALI, Martin G. DIXON
  • Publication number: 20170147340
    Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
    Type: Application
    Filed: December 31, 2016
    Publication date: May 25, 2017
    Inventors: Kirk S. YAP, Gilbert M. WOLRICH, James D. GUILFORD, Vinodh GOPAL, Erdinc OZTURK, Sean M. GULLEY, Wajdi K. FEGHALI, Martin G. DIXON