Abstract: An optical or an optoelectronic device and methods are provided for data transmission across two interconnects. First, an electrical signal is obtained from an interconnect. Next, the electrical signal is modulated. Within the modulated electrical signal, an occurrence of a transition is determined, in which a change in a power of the electrical signal by more than a threshold amount. In response to the determination of the occurrence of the transition, coefficients indicative of respective amounts of compensation to resolve or mitigate nonlinearities associated with the transition are determined. According to the coefficients, a filter is applied in a vicinity of the transition to obtain a modified electrical signal. The modified electrical signal is converted into an optical signal and coupled to a fiber to transmit the optical signal to a destination at a second interconnect.

Abstract: An optical or an optoelectronic device and methods are provided for data transmission across two interconnects. First, an electrical signal is obtained from an interconnect. Next, the electrical signal is modulated. Within the modulated electrical signal, an occurrence of a transition is determined, in which a change in a power of the electrical signal by more than a threshold amount. In response to the determination of the occurrence of the transition, coefficients indicative of respective amounts of compensation to resolve or mitigate nonlinearities associated with the transition are determined. According to the coefficients, a filter is applied in a vicinity of the transition to obtain a modified electrical signal. The modified electrical signal is converted into an optical signal and coupled to a fiber to transmit the optical signal to a destination at a second interconnect.

Abstract: A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes utilizes latches where flops were previously used to help reduce power consumption, among other things. The SerDes also includes a main register bank with a plurality of sub-banks that can be filled according to any number of different schemes, thereby enabling the SerDes to accommodate different output widths.

Abstract: A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes utilizes latches where flops were previously used to help reduce power consumption, among other things. The SerDes also includes a main register bank with a plurality of sub-banks that can be filled according to any number of different schemes, thereby enabling the SerDes to accommodate different output widths.

Abstract: An N-phase clock generation circuit includes an input clock signal comprising a first phase signal, a phase interpolator configured to receive the input clock signal and generate a second phase signal, a first divider element configured to receive the first phase signal and generate an in-phase divided clock signal, a second divider element configured to receive the second phase signal and generate a quadrature divided clock signal, a first delay element configured to receive the in-phase divided clock signal and an in-phase control signal, the first delay element configured to generate a delayed in-phase divided clock signal, an a second delay element configured to receive the quadrature divided clock signal and a quadrature control signal, the second delay element configured to generate a delayed quadrature divided clock signal.

Abstract: A serial-to-parallel converter includes a first register bank having first and second register groups, the first register bank configured to receive a communication signal having at least one bit for each unit interval (UI) of a system clock signal, the first register bank having a number of registers corresponding to a number of parallel processing stages, a second register bank having a plurality of register groups, each register group configured to receive the output of at least one of the first and second register groups after a number of unit intervals corresponding to the number of registers in each of the first and second register groups in the first register bank, and a third register bank configured to receive the output of the second register bank after a number of unit intervals corresponding to a number of registers in the second register bank.

Abstract: An apparatus for generating a constant logical value in an integrated circuit includes a first logic network having n outputs, the n outputs providing 2n possible output combinations, where the n outputs assume a state that is a subset of the 2n possible output combinations and a second logic network configured to generate at least one constant logic signal when the n outputs assume any state that is part of the subset of the 2n possible output combinations.

Abstract: An apparatus for generating a constant logical value in an integrated circuit includes a first logic network having n outputs, the n outputs providing 2n possible output combinations, where the n outputs assume a state that is a subset of the 2n possible output combinations and a second logic network configured to generate at least one constant logic signal when the n outputs assume any state that is part of the subset of the 2n possible output combinations.

Abstract: A second single-ended receiver having a first stage for receiving an input signal and outputting a pair of corresponding output signals, and a second stage for receiving the pair of output signals and outputting a corresponding single output signal. First and second pull-down transistors are coupled to first and second inputs to the first stage. A bias circuit electrically biases the first stage, second stage, and first and second pull-down transistors, and a power supply provides power to those components.

Abstract: A system and method for providing a clock signal and data signal delay match to improve setup and hold times for integrated circuits is disclosed. In a simplified embodiment, the system comprises a clock receiver capable of removing noise from a received clock signal. A clock buffer is connected to the clock receiver and is capable of driving the received clock signal to a register. A data receiver is located within the system which is capable of removing noise from received data. In addition at least one miniature clock buffer is located within the system, wherein the at least one miniaturized clock buffer is a scaled version of the clock buffer having a scaling factor of K, the scaling factor representing a number of miniature clock buffers utilized to minimize negative variations experienced by the clock buffer.

Abstract: A simultaneous switching noise (SSN) test circuit and method are provided for measuring effects of SSN. Prior to testing for SSN, a signal is applied to the victim signal input pad and the rise and fall time delays associated with the victim signal are measured at the victim signal output pad. Then, one or more aggressor signals are simultaneously applied to respective input pads of one or more respective aggressor signal paths. The rise and fall time delays of the victim signal transmitted by the output pad are then measured and compared to the previously measured rise and fall time delays to determine effects of SSN on the victim signal caused by the aggressor signals.

Abstract: A second single-ended receiver having a first stage for receiving an input signal and outputting a pair of corresponding output signals, and a second stage for receiving the pair of output signals and outputting a corresponding single output signal. First and second pull-down transistors are coupled to first and second inputs to the first stage. A bias circuit electrically biases the first stage, second stage, and first and second pull-down transistors, and a power supply provides power to those components.

Abstract: A simultaneous switching noise (SSN) test circuit and method are provided for measuring effects of SSN. Prior to testing for SSN, a signal is applied to the victim signal input pad and the rise and fall time delays associated with the victim signal are measured at the victim signal output pad. Then, one or more aggressor signals are simultaneously applied to respective input pads of one or more respective aggressor signal paths. The rise and fall time delays of the victim signal transmitted by the output pad are then measured and compared to the previously measured rise and fall time delays to determine effects of SSN on the victim signal caused by the aggressor signals.

Abstract: A novel terminating differential bus receiver with automatic compensation for process, voltage, and temperature variation is presented. A termination circuit is connected internal to the integrated circuit to the input of a differential receiver in parallel with a transmission line connectable to the receiver. Both the termination circuit and the differential receiver are implemented with at least one p-channel transistor and at least one n-channel transistor, such that the p-channel transistors of the termination circuit and receiver and the n-channel transistors of the termination circuit and receiver are ratioed to vary similarly under PVT variation.

Abstract: An active termination technique for reducing the propagation delay of a signal across a transmission line is presented. In accordance with a preferred embodiment of the invention, repeaters along a transmission line are paired with active termination circuits in very close proximity to the repeater in order to prevent signal reflections caused by the repeaters. The repeaters and associated active termination circuits are implemented with at least one PFET and at least one NFET, each having the same transistor gate lengths. The PFETs and the NFETs in the repeater and associated termination are ratioed to vary similarly over process/voltage/temperature variation.

Abstract: An active termination technique for reducing the propagation delay of a signal across a transmission line is presented. In accordance with a preferred embodiment of the invention, repeaters along a transmission line are paired with active termination circuits in very close proximity to the repeater in order to prevent signal reflections caused by the repeaters. The repeaters and associated active termination circuits are implemented with at least one PFET and at least one NFET, each having the same transistor gate lengths. The PFETs and the NFETs in the repeater and associated termination are ratioed to vary similarly over process/voltage/temperature variation.

Abstract: A novel terminating differential bus receiver with automatic compensation for process, voltage, and temperature variation is presented. A termination circuit is connected internal to the integrated circuit to the input of a differential receiver in parallel with a transmission line connectable to the receiver. Both the termination circuit and the differential receiver are implemented with at least one p-channel transistor and at least one n-channel transistor, such that the p-channel transistors of the termination circuit and receiver and the n-channel transistors of the termination circuit and receiver are ratioed to vary similarly under PVT variation.

Abstract: A system and method for providing a clock signal and data signal delay match to improve setup and hold times for integrated circuits is disclosed. In a simplified embodiment, the system comprises a clock receiver capable of removing noise from a received clock signal. A clock buffer is connected to the clock receiver and is capable of driving the received clock signal to a register. A data receiver is located within the system which is capable of removing noise from received data. In addition at least one miniature clock buffer is located within the system, wherein the at least one miniaturized clock buffer is a scaled version of the clock buffer having a scaling factor of K, the scaling factor representing a number of miniature clock buffers utilized to minimize negative variations experienced by the clock buffer.