Abstract: The present invention provides a memory device of MNOS FET type wherein a high concentration part and a low concentration part contact each other in the source region and the drain region, and further, double layered insulation films under the gate electrode extending across the source region and drain region are made to contact only the lower concentration part, so that an acceptor impurity is prevented from mixing into the double layered insulation films from the source region and drain region, thus greatly improving the life (number of repeated uses) of the device.

Abstract: A silicon oxide layer containing a group III element such as boron, aluminum or gallium is formed on a semiconductor substrate. The substrate is then heat treated at 600.degree. C - 1200.degree. C in a nitrogen atmosphere and a diffusion process carried out thereafter. In this manner, the impurity diffused surface of the semiconductor body is controlled to a low concentration not higher than 10.sup.18 /cm.sup.3 of the group III element. This is due to the fact that the silicon oxide layer containing the group III element (that is, the so-called doped oxide) is partly converted to a nitride in the course of an ammonia treatment resulting in an impurity source for the low concentration diffusion. The present method is useful in forming the base region of an NPN transistor, for example.