Patents by Inventor Girisankar Paulraj
Girisankar Paulraj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11036406Abstract: Managing system memory allocation according to a thermal profile defining memory segment policies according to power, performance, and thermal requirements, selecting a defined memory segment policy, implementing a system workload according to the memory segment policy and deploying the system workload according to the implemented memory segment policy.Type: GrantFiled: May 21, 2019Date of Patent: June 15, 2021Assignee: International Business Machines CorporationInventors: Girisankar Paulraj, Daniel Lewis, Sumantra Sarkar, Arindam Raychaudhuri, Diyanesh B. Chinnakkonda Vidyapoornachary
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Publication number: 20200371699Abstract: Managing system memory allocation according to a thermal profile defining memory segment policies according to power, performance, and thermal requirements, selecting a defined memory segment policy, implementing a system workload according to the memory segment policy and deploying the system workload according to the implemented memory segment policy.Type: ApplicationFiled: May 21, 2019Publication date: November 26, 2020Inventors: Girisankar Paulraj, Daniel Lewis, Sumantra Sarkar, Arindam Raychaudhuri, Diyanesh B. Chinnakkonda Vidyapoornachary
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Patent number: 10564866Abstract: According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A second error is detected in the first bank number of a second memory device of the rank. Access requests for the first bank number of the second memory device are steered to the non-faulty bank having the second bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition by correcting the first error using an error-correcting code decoder.Type: GrantFiled: November 21, 2017Date of Patent: February 18, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy J. Dell, Girisankar Paulraj, Diyanesh B. Chinnakkonda Vidyapoornachary
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Publication number: 20180074734Abstract: According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A second error is detected in the first bank number of a second memory device of the rank. Access requests for the first bank number of the second memory device are steered to the non-faulty bank having the second bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition by correcting the first error using an error-correcting code decoder.Type: ApplicationFiled: November 21, 2017Publication date: March 15, 2018Inventors: Timothy J. Dell, Girisankar Paulraj, Diyanesh B. Chinnakkonda Vidyapoornachary
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Patent number: 9857993Abstract: According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including a plurality of memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition.Type: GrantFiled: October 6, 2014Date of Patent: January 2, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy J. Dell, Girisankar Paulraj, Diyanesh B.Chinnakkonda Vidyapoornachary
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Patent number: 9606944Abstract: A first memory buffer has a first high speed memory channel and a second high speed memory channel. A second memory buffer is connected to the first memory buffer through a first connection. The second memory buffer has a third high speed memory channel and a fourth high speed memory channel. The first connection connects the first high speed memory channel and the third high speed memory channel. A first memory controller is connected to the first memory buffer through the second high speed memory channel. A second memory controller is connected to the second memory buffer through a second connection. The second connection is connected to the second memory buffer through the fourth high speed memory channel. A first memory module set is connected to the first memory buffer and a second memory module set is connected to the second memory buffer.Type: GrantFiled: March 20, 2014Date of Patent: March 28, 2017Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Girisankar Paulraj, Diyanesh B. Chinnakkonda Vidyapoornachary
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Patent number: 9600187Abstract: The present disclosure includes identifying, in a memory system, a capacity for each of a plurality of memory modules for a first memory channel having a first amount of memory and a second memory channel having a second amount of memory; determining a memory segment size from the capacities of the memory modules; identifying a first memory segment of the memory segment size for the first memory channel and a second memory segment of the memory segment size for the second memory channel; and creating a virtual group that includes the first memory segment and the second memory segment and that uses less than the entire first amount of memory from the first memory channel.Type: GrantFiled: August 23, 2016Date of Patent: March 21, 2017Assignee: International Business Machines CorporationInventors: Timothy J. Dell, Prasanna Jayaraman, Anil B. Lingambudi, Girisankar Paulraj
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Patent number: 9600189Abstract: According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including a plurality of memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition.Type: GrantFiled: June 11, 2014Date of Patent: March 21, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy J. Dell, Girisankar Paulraj, Diyanesh B.Chinnakkonda Vidyapoornachary
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Publication number: 20160357459Abstract: The present disclosure includes identifying, in a memory system, a capacity for each of a plurality of memory modules for a first memory channel having a first amount of memory and a second memory channel having a second amount of memory; determining a memory segment size from the capacities of the memory modules; identifying a first memory segment of the memory segment size for the first memory channel and a second memory segment of the memory segment size for the second memory channel; and creating a virtual group that includes the first memory segment and the second memory segment and that uses less than the entire first amount of memory from the first memory channel.Type: ApplicationFiled: August 23, 2016Publication date: December 8, 2016Inventors: Timothy J. Dell, Prasanna Jayaraman, Anil B. Lingambudi, Girisankar Paulraj
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Patent number: 9501432Abstract: A first memory buffer has a first high speed memory channel and a second high speed memory channel. A second memory buffer is connected to the first memory buffer through a first connection. The second memory buffer has a third high speed memory channel and a fourth high speed memory channel. The first connection connects the first high speed memory channel and the third high speed memory channel. A first memory controller is connected to the first memory buffer through the second high speed memory channel. A second memory controller is connected to the second memory buffer through a second connection. The second connection is connected to the second memory buffer through the fourth high speed memory channel. A first memory module set is connected to the first memory buffer and a second memory module set is connected to the second memory buffer.Type: GrantFiled: April 7, 2014Date of Patent: November 22, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Girisankar Paulraj, Diyanesh B. Chinnakkonda Vidyapoornachary
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Patent number: 9471540Abstract: A computer determines a threshold signal voltage of a semiconductor device. The computer determines a first expected signal propagation time for a signal travelling through a first test path of the semiconductor device. The computer transmits a first signal through the first test path. The computer measures a signal voltage and signal propagation time of the first signal. The computer determines that the signal voltage of the first signal does not reach or exceed the threshold signal voltage within the first expected signal propagation time. The computer determines that the first test path contains a defect.Type: GrantFiled: January 3, 2013Date of Patent: October 18, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edgar R. Cordero, Anand Haridass, Girisankar Paulraj, Diyanesh B. Vidyapoornachary
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Patent number: 9442816Abstract: A method, system and computer program product implement memory performance management and enhanced memory reliability of a computer system accounting for system thermal conditions. When a primary memory temperature reaches an initial temperature threshold, reads are suspended to the primary memory and reads are provided to a mirrored memory in a mirrored memory pair, and writes are provided to both the primary memory and the mirrored memory. If the primary memory temperature reaches a second temperature threshold, write operations to the primary memory are also stopped and the primary memory is turned off with DRAM power saving modes such as self timed refresh (STR), and the reads and writes are limited to the mirrored memory in the mirrored memory pair. When the primary memory temperature decreases to below the initial temperature threshold, coherency is recovered by writing a coherent copy from the mirrored memory to the primary memory.Type: GrantFiled: November 30, 2011Date of Patent: September 13, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Anil B. Lingambudi, Girisankar Paulraj, Diyanesh B. Vidyapoornachary
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Patent number: 9342700Abstract: A method, system and memory controller for implementing enhanced security in a memory subsystem including DRAM in a computer system. A memory includes a register to hold scrambling information transmitted from a memory controller; and scrambling circuitry on the memory to scramble at least one of bank select bits and data bits responsive to the scrambling information in the register.Type: GrantFiled: June 16, 2014Date of Patent: May 17, 2016Assignee: International Business Machines CorporationInventors: Timothy J. Dell, Prasanna Jayaraman, Girisankar Paulraj, Diyanesh Babu C. Vidyapoornachary
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Patent number: 9336401Abstract: A method, system and memory controller for implementing enhanced security in a memory subsystem including DRAM in a computer system. A memory includes a register to hold scrambling information transmitted from a memory controller; and scrambling circuitry on the memory to scramble at least one of bank select bits and data bits responsive to the scrambling information in the register.Type: GrantFiled: January 20, 2014Date of Patent: May 10, 2016Assignee: International Business Machines CorporationInventors: Timothy J. Dell, Prasanna Jayaraman, Girisankar Paulraj, Diyanesh Babu C. Vidyapoornachary
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Patent number: 9330737Abstract: A memory controller enters a memory mode, allocating memory address space within a pair of dual in line memory modules (DIMMs) such that each DIMM of the pair contains unallocated memory address space corresponding to allocated memory space in the other DIMM. The memory controller enters another memory mode, modifying the allocation of the memory address space from a first DIMM of the pair of DIMMs to a second DIMM of the pair of DIMMs. The data is moved from allocated memory address space of the first DIMM to unallocated memory address space in the second DIMM.Type: GrantFiled: May 30, 2014Date of Patent: May 3, 2016Assignee: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Prasanna Jayaraman, Girisankar Paulraj
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Patent number: 9329648Abstract: An approach is provided in which a subsystem cooling manager detects an increased workload indicator corresponding to a computer subsystem's forthcoming workload requirement. The forthcoming workload requirement corresponds to future computing resources required by the subsystem to support one or more software programs executing on the computer system. The subsystem cooling manager determines that the forthcoming workload requirement exceeds a utilization threshold and in turn, directs one or more cooling systems towards the corresponding subsystem according.Type: GrantFiled: July 17, 2012Date of Patent: May 3, 2016Assignee: International Business Machines CorporationInventors: Diyanesh Babu Vidyapoornachary Chinnakkonda, Edgar Rolando Cordero, Timothy J. Dell, Joab D. Henderson, Anil B. Lingambudi, Girisankar Paulraj
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Patent number: 9324388Abstract: A memory controller enters a memory mode, allocating memory address space within a pair of dual in line memory modules (DIMMs) such that each DIMM of the pair contains unallocated memory address space corresponding to allocated memory space in the other DIMM. The memory controller enters another memory mode, modifying the allocation of the memory address space from a first DIMM of the pair of DIMMs to a second DIMM of the pair of DIMMs. The data is moved from allocated memory address space of the first DIMM to unallocated memory address space in the second DIMM.Type: GrantFiled: March 27, 2014Date of Patent: April 26, 2016Assignee: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Prasanna Jayaraman, Girisankar Paulraj
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Publication number: 20150363255Abstract: According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including a plurality of memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition.Type: ApplicationFiled: June 11, 2014Publication date: December 17, 2015Inventors: Timothy J. Dell, Girisankar Paulraj, Diyanesh B.Chinnakkonda Vidyapoornachary
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Publication number: 20150363287Abstract: According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including a plurality of memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition.Type: ApplicationFiled: October 6, 2014Publication date: December 17, 2015Inventors: Timothy J. Dell, Girisankar Paulraj, Diyanesh B.Chinnakkonda Vidyapoornachary
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Publication number: 20150279461Abstract: A memory controller enters a memory mode, allocating memory address space within a pair of DIMMs such that each DIMM of the pair contains unallocated memory address space corresponding to allocated memory space in the other DIMM. The memory controller enters another memory mode, modifying the allocation of the memory address space from a first DIMM of the pair of DIMMs to a second DIMM of the pair of DIMMs. The data is moved from allocated memory address space of the first DIMM to unallocated memory address space in the second DIMM.Type: ApplicationFiled: May 30, 2014Publication date: October 1, 2015Applicant: International Business Machines CorporationInventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Prasanna Jayaraman, Girisankar Paulraj