Patents by Inventor Girishankar Gurumurthy
Girishankar Gurumurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220052694Abstract: An isolation circuit includes an inverter and a NOR-gate. The inverter includes an input terminal used to receive an input signal, an output terminal used to output an output signal according to the input signal, and a power terminal coupled to a power supply. The output signal is complementary to the input signal. The NOR-gate is used to perform a logic NOR operation using the output signal and an isolation control signal to generate a result signal. The NOR-gate includes a first input terminal coupled to the output terminal of the inverter for receiving the output signal, a second input terminal for receiving the isolation control signal, and an output terminal for outputting the result signal.Type: ApplicationFiled: August 17, 2020Publication date: February 17, 2022Inventors: Varinder Kumar, Heerak Bandopadhyay, Girishankar Gurumurthy, Aakash Srivastava, Ramesh SrinivasRao Guzar
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Patent number: 10126363Abstract: A flip-flop circuit is provided. The flip-flop circuit receives a test signal at a test-in terminal and a data signal at a data-in terminal and generates a scan-out signal. The flip-flop circuit includes a buffer and a scan flip-flop. The buffer has an input terminal coupled to the test-in terminal and an output terminal and further has a first power terminal and a second power terminal. The buffer operates to generate a buffering signal. The scan flip-flop receives the buffering signal and the data signal. The scan flip-flop is controlled by a test-enable signal to generate the scan-out signal according to the buffering signal or the data signal. The scan flip-flop further generates a test-enable reverse signal which is the reverse of the test-enable signal. The first power terminal of the buffer receives the test-enable signal or the test-enable reverse signal.Type: GrantFiled: July 12, 2017Date of Patent: November 13, 2018Assignee: MEDIATEK INC.Inventors: Wen-Yi Lin, Girishankar Gurumurthy
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Publication number: 20180224505Abstract: A flip-flop circuit is provided. The flip-flop circuit receives a test signal at a test-in terminal and a data signal at a data-in terminal and generates a scan-out signal. The flip-flop circuit includes a buffer and a scan flip-flop. The buffer has an input terminal coupled to the test-in terminal and an output terminal and further has a first power terminal and a second power terminal. The buffer operates to generate a buffering signal. The scan flip-flop receives the buffering signal and the data signal. The scan flip-flop is controlled by a test-enable signal to generate the scan-out signal according to the buffering signal or the data signal. The scan flip-flop further generates a test-enable reverse signal which is the reverse of the test-enable signal. The first power terminal of the buffer receives the test-enable signal or the test-enable reverse signal.Type: ApplicationFiled: July 12, 2017Publication date: August 9, 2018Inventors: Wen-Yi LIN, Girishankar GURUMURTHY
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Patent number: 9419014Abstract: An integrated circuit includes a plurality of N wells disposed on a P substrate. A plurality of tap columns is located across the plurality of N wells and a plurality of standard cells is located between the tap columns. A plurality of tap cells is disposed consecutively in the plurality of tap columns. Each tap cell further includes a first tap active and a second tap active. The first tap active of a first tap cell extends to the first tap active of a second tap cell which further extends to a well boundary of either the first tap cell or the second tap cell. The first tap active of the first tap cell and the first tap active of the second tap cell are adjacent to each other in the tap column.Type: GrantFiled: December 17, 2013Date of Patent: August 16, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Girishankar Gurumurthy
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Patent number: 9366727Abstract: A scan flip flop includes a partial multiplexer coupled to a master latch. The partial multiplexer is configured to receive a scan enable (SCAN) where the partial multiplexer includes an OR gate coupled to a tri-stated AND gate. A tri-state inverter is coupled to an output of the master latch and a slave latch is configured to receive an output of the tri-state inverter. A delay element is coupled to the slave latch, where the delay element is configured to delay a first output of the slave latch in response to the scan enable to generate a dedicated scan output.Type: GrantFiled: December 16, 2013Date of Patent: June 14, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Girishankar Gurumurthy
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Patent number: 9362910Abstract: In an integrated clock gating (ICG) cell a latch is coupled to a NOR gate. The NOR gate receives an enable signal. The latch is configured to generate a latch output in response to the state of the enable signal. The latch includes a tri-state inverter. A NAND gate is coupled to the latch and the NAND gate is configured to generate an inverted clock signal in response to the latch output and a clock input.Type: GrantFiled: November 25, 2013Date of Patent: June 7, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Girishankar Gurumurthy, Mahesh Ramdas Vasishta
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Patent number: 9331680Abstract: A flip-flop that includes a multiplexer configured to generate a multiplexer output. The multiplexer output is generated in response to an input and a scan enable, and is given to a transmission gate. A master latch is coupled to the transmission gate and to a tri-state inverter. The master latch is configured to receive an output of the transmission gate. A slave latch is configured to receive an output of the tri-state inverter and the multiplexer output. A data inverter is coupled to the slave latch. The data inverter is configured to generate a flip-flop output. A half clock gating inverter is configured to generate an inverted clock input in response to a clock input and the multiplexer output.Type: GrantFiled: September 10, 2014Date of Patent: May 3, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Girishankar Gurumurthy, Mahesh Ramdas Vasishta
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Publication number: 20150070063Abstract: A flip-flop that includes a multiplexer configured to generate a multiplexer output. The multiplexer output is generated in response to an input and a scan enable, and is given to a transmission gate. A master latch is coupled to the transmission gate and to a tri-state inverter. The master latch is configured to receive an output of the transmission gate. A slave latch is configured to receive an output of the tri-state inverter and the multiplexer output. A data inverter is coupled to the slave latch. The data inverter is configured to generate a flip-flop output. A half clock gating inverter is configured to generate an inverted clock input in response to a clock input and the multiplexer output.Type: ApplicationFiled: September 10, 2014Publication date: March 12, 2015Applicant: Texas Instruments IncorporatedInventors: Girishankar Gurumurthy, Mahesh Ramdas Vasishta
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Publication number: 20140189453Abstract: A scan flip flop includes a partial multiplexer coupled to a master latch. The partial multiplexer is configured to receive a scan enable (SCAN) where the partial multiplexer includes an OR gate coupled to a tri-stated AND gate. A tri-state inverter is coupled to an output of the master latch and a slave latch is configured to receive an output of the tri-state inverter. A delay element is coupled to the slave latch, where the delay element is configured to delay a first output of the slave latch in response to the scan enable to generate a dedicated scan output.Type: ApplicationFiled: December 16, 2013Publication date: July 3, 2014Inventor: Girishankar Gurumurthy
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Publication number: 20140183602Abstract: An integrated circuit includes a plurality of N wells disposed on a P substrate. A plurality of tap columns is located across the plurality of N wells and a plurality of standard cells is located between the tap columns. A plurality of tap cells is disposed consecutively in the plurality of tap columns. Each tap cell further includes a first tap active and a second tap active. The first tap active of a first tap cell extends to the first tap active of a second tap cell which further extends to a well boundary of either the first tap cell or the second tap cell. The first tap active of the first tap cell and the first tap active of the second tap cell are adjacent to each other in the tap column.Type: ApplicationFiled: December 17, 2013Publication date: July 3, 2014Inventor: Girishankar Gurumurthy
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Publication number: 20140184271Abstract: In an integrated clock gating (ICG) cell a latch is coupled to a NOR gate. The NOR gate receives an enable signal. The latch is configured to generate a latch output in response to the state of the enable signal. The latch includes a tri-state inverter. A NAND gate is coupled to the latch and the NAND gate is configured to generate an inverted clock signal in response to the latch output and a clock input.Type: ApplicationFiled: November 25, 2013Publication date: July 3, 2014Inventors: Girishankar Gurumurthy, Mahesh Ramdas Vasishta
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Patent number: 8578224Abstract: A master/slave latch includes an input stage, a master latch, a slave latch, and receives an asynchronous clear signal. The input stage is arranged to alternately pass or block a data input signal in response to a clock signal and a gated clock signal. The gated clock signal is the inverse of the clock signal when the asynchronous clear signal is not asserted, and the gated clock signal is not active when the asynchronous clear signal is asserted. The master latch receives and latches the passed data signal in a latched state, clears the latched state in response to the asynchronous clear signal being asserted, and generates a master latch output signal. The slave latch receives and latches the master latch output signal in a latched state. The cleared latched state is passed to the slave latch in response to the asynchronous clear signal being asserted.Type: GrantFiled: December 31, 2011Date of Patent: November 5, 2013Assignee: Texas Instruments IncorporatedInventors: Girishankar Gurumurthy, Mahesh Ramdas Vasishta
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Publication number: 20130173977Abstract: A master/slave latch includes an input stage, a master latch, a slave latch, and receives an asynchronous clear signal. The input stage is arranged to alternately pass or block a data input signal in response to a clock signal and a gated clock signal. The gated clock signal is the inverse of the clock signal when the asynchronous clear signal is not asserted, and the gated clock signal is not active when the asynchronous clear signal is asserted. The master latch receives and latches the passed data signal in a latched state, clears the latched state in response to the asynchronous clear signal being asserted, and generates a master latch output signal. The slave latch receives and latches the master latch output signal in a latched state. The cleared latched state is passed to the slave latch in response to the asynchronous clear signal being asserted.Type: ApplicationFiled: December 31, 2011Publication date: July 4, 2013Applicant: Texas Instruments IncorporatedInventors: Girishankar Gurumurthy, Mehesh Ramdas Vasishta
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Patent number: 8127263Abstract: Improving routability of an integrated circuit (IC) design without impacting the area is described. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion.Type: GrantFiled: February 3, 2009Date of Patent: February 28, 2012Assignee: Texas Instruments IncorporatedInventors: Pavan Vithal Torvi, Girishankar Gurumurthy, Dharin N Shah, Ajith Harihara Subramonia
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Patent number: 8112737Abstract: A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical cells of the library cells are selected. The selected critical cells are altered with respect to contact resistance and/or contact capacitance. The map including the altered cells is provided as the design layout.Type: GrantFiled: September 19, 2008Date of Patent: February 7, 2012Assignee: Texas Instruments IncorporatedInventors: Nagaraj N. Savithri, Dharin Nayeshbhai Shah, Girishankar Gurumurthy
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Patent number: 7895551Abstract: Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed buses may also be removed. Additional via and connections are added to other desired layers to provide connectivity to the nodes disconnected due to the earlier removal. According to an aspect of the present invention, such connections are added during a chip design phase (i.e., when the cell instances are incorporated into an integrated circuit, sought to be designed).Type: GrantFiled: May 21, 2008Date of Patent: February 22, 2011Assignee: Texas Instruments IncorporatedInventors: Dharin Shah, Clive David Bittlestone, Graham McLeod Barr, Girishankar Gurumurthy, Pavan Vithal Torvi
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Publication number: 20100199252Abstract: Improving the routability of integrated circuit (IC) design without impacting the area. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion.Type: ApplicationFiled: February 3, 2009Publication date: August 5, 2010Inventors: Pavan Vithal Torvi, Girishankar Gurumurthy, Dharin N. Shah, Ajith Harihara Subramonia
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Publication number: 20090293023Abstract: Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed buses may also be removed. Additional via and connections are added to other desired layers to provide connectivity to the nodes disconnected due to the earlier removal. According to an aspect of the present invention, such connections are added during a chip design phase (i.e., when the cell instances are incorporated into an integrated circuit, sought to be designed).Type: ApplicationFiled: May 21, 2008Publication date: November 26, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Dharin Shah, Clive David Bittlestone, Graham McLeod Barr, Girishankar Gurumurthy, Pavan Vithal Torvi
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Patent number: 7564077Abstract: An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.Type: GrantFiled: May 7, 2007Date of Patent: July 21, 2009Assignee: Texas Instruments IncorporatedInventors: Uming Ko, Dharin Shah, Senthil Sundaramoorthy, Girishankar Gurumurthy, Sumanth Gururajarao, Rolf Lagerquist, Clive Bittlestone
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Patent number: 7483819Abstract: Determining piece-wise polynomials which together would represent large data sets having multi-dimensional input vectors and corresponding output element. In an embodiment, a function/procedure/routine is recursively called/invoked to determine piece-wise polynomial is a data set cannot be entirely modeled by one polynomial. Another aspect of the present invention reduces the number of combinations (of orders for sub-polynomials forming the polynomials) to be tried in determining polynomials, meeting various accuracy requirements. Such a reduction is obtained based on a recognition that when the order in one dimension alone is increased and the result does not lead to acceptable accuracy of the polynomial, the combinations with a lesser number for the order (of the dimension) can be ruled out.Type: GrantFiled: December 7, 2004Date of Patent: January 27, 2009Assignee: Texas Instruments IncorporatedInventors: Girishankar Gurumurthy, Shitanshu Krishnachandra Tiwari, Hugh Thomas Mair, Sumanth K Gururajarao