Abstract: A method for controlling a BLDC motor includes controlling the rotational speed or position of the BLDC motor based on a position of the rotor of the motor. The BLDC motor is driven by a three-phase inverter. A PWM signal is generated for three PWM phases, each including a pair of complementary signals with dead-time and having a duty cycle based on the current position of the rotor. The complementary signals are supplied to a respective high side and low side switch of each of three arms of the three-phase inverter, and a zero-crossing time measurement is performed on each of the back electromotive forces. Corresponding signals are obtained indicating the zero-crossing times. Trigger signals are generated, and the occurrence of a time interval corresponding to the dead time in the respective PWM phase is identified. The zero-crossing time measurement is performed during the occurrence of the dead-time.

Abstract: In an embodiment, a circuit includes first and second analog-to-digital conversion circuit path. The first analog-to-digital conversion circuit path is configured to provide first converted digital data from an analog input signal. The second analog-to-digital conversion circuit path is configured to provide second converted digital data from the analog input signal. A comparison circuit is configured to compare the first converted digital data with the second converter digital data and generate a fault based on the comparison to reveal a mismatch between the first and second converted digital data.

Abstract: A time capture circuit can measure time between edges of a logic input signal. A delay line generates consecutive increasingly delayed replicas of the logic input signal. A free running counter is clocked by a counter clock signal corresponding to an external clock signal multiplied by a clock scale factor. A counter value capture circuit captures the counter value upon occurrence of an edge in the input signal, outputs a captured counter value, and issues a trigger signal. A decoder determines a decoded value based on values of the input signal and of the plurality of consecutive increasingly replicas when the trigger signal is issued and computes a capture value as the difference of the captured counter value logical left shifted by a first scale factor and the decoded value logical right shifted by a second scale factor.

Abstract: A half-bridge driver circuit includes an amplifier configured to generate a measurement signal indicative of a current flowing through a shunt resistor. A processing circuit is configured to selectively acquire a sample of the measurement signal in response to a trigger signal. A synchronization circuit is configured to determine a first value indicative of the switch-on duration of a high side control signal, determine a second value indicative of the switching period of the high side control signal, compute a third value based on the first and second values, generate a third signal based on the third value when the next switching period of the high side control signal starts, start a second counter in response to the third signal, compare the count value of the second counter with a reference value to generate a fourth signal, and generate the trigger signal as a function of the fourth signal.

Abstract: Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.

Abstract: A method for performing a noise removal operation includes decomposing an acquired signal considered as one dimensional series. A trajectory matrix is constructed, transforming the trajectory matrix in a form to which single value decomposition is applicable. A single value decomposition is done on the transformed matrix computing eigenvalues and eigenvectors of the matrix. A one dimensional series is reconstructed, corresponding to the denoised signal. After the single value decomposition operation is provided, a single value decomposition is applied sequentially starting from a given window value. For each iteration, the root mean square value is calculated between a current and previous eigenvalue, calculating a minimum and its position of said root mean square value. The iterations are halted if the minimum is lower than a determined threshold value, otherwise increasing the window value and returning to the operation of decomposition of the acquired signal.

Abstract: A time capture circuit can measure time between edges of a logic input signal. A delay line generates consecutive increasingly delayed replicas of the logic input signal. A free running counter is clocked by a counter clock signal corresponding to an external clock signal multiplied by a clock scale factor. A counter value capture circuit captures the counter value upon occurrence of an edge in the input signal, outputs a captured counter value, and issues a trigger signal. A decoder determines a decoded value based on values of the input signal and of the plurality of consecutive increasingly replicas when the trigger signal is issued and computes a capture value as the difference of the captured counter value logical left shifted by a first scale factor and the decoded value logical right shifted by a second scale factor.

Abstract: Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.

Abstract: A half-bridge driver circuit is configured to generate drive signals based on control signals. A processing circuit is configured to generate high side and low side control signals based on a control signal. An edge detector is configured to generate first and second signals in response to rising and falling edges in the control signal. A state machine transitions between states in response to the first and second signals, and is configured to sequentially, in response to the first signal, set the high side and low side control signals low; in response to the second signal, set the high side control signal high and the low side control signal low; in response to the first signal, set the high side and low side control signals low; and in response to the second signal, set the high side control signal low and the low side control signal high.

Abstract: In an embodiment, a circuit includes first and second analog-to-digital conversion circuit path. The first analog-to-digital conversion circuit path is configured to provide first converted digital data from an analog input signal. The second analog-to-digital conversion circuit path is configured to provide second converted digital data from the analog input signal. A comparison circuit is configured to compare the first converted digital data with the second converter digital data and generate a fault based on the comparison to reveal a mismatch between the first and second converted digital data.

Abstract: Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.

Abstract: An electric motor is controlled by means of pulse-width modulated control signal having edge transitions occurring at certain transition count values of the pulses of a clock signal which is frequency-modulated with a step-wise frequency modulation (e.g., SSCG or Spread Spectrum Clock Generation). A frequency unmodulated clock signal is provided having a fixed period indicative of the period of the pulse-width modulated control signals. The transition count values are set as a function of a predicted count value and/or a predicted frequency value for the frequency-modulated clock signal. Prediction occurs as a function of the frequency unmodulated clock signal, so that the transition count values are compensated against the step-wise (e.g., SSCG) frequency modulation.

Abstract: A half-bridge driver circuit is configured to generate drive signals based on control signals. A processing circuit is configured to generate high side and low side control signals based on a control signal. An edge detector is configured to generate first and second signals in response to rising and falling edges in the control signal. A state machine transitions between states in response to the first and second signals, and is configured to sequentially, in response to the first signal, set the high side and low side control signals low; in response to the second signal, set the high side control signal high and the low side control signal low; in response to the first signal, set the high side and low side control signals low; and in response to the second signal, set the high side control signal low and the low side control signal high.

Abstract: A half-bridge driver circuit includes an amplifier configured to generate a measurement signal indicative of a current flowing through a shunt resistor. A processing circuit is configured to selectively acquire a sample of the measurement signal in response to a trigger signal. A synchronization circuit is configured to determine a first value indicative of the switch-on duration of a high side control signal, determine a second value indicative of the switching period of the high side control signal, compute a third value based on the first and second values, generate a third signal based on the third value when the next switching period of the high side control signal starts, start a second counter in response to the third signal, compare the count value of the second counter with a reference value to generate a fourth signal, and generate the trigger signal as a function of the fourth signal.

Abstract: Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.

Abstract: Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.

Abstract: A method for performing a noise removal operation includes decomposing an acquired signal considered as one dimensional series. A trajectory matrix is constructed, transforming the trajectory matrix in a form to which single value decomposition is applicable. A single value decomposition is done on the transformed matrix computing eigenvalues and eigenvectors of the matrix. A one dimensional series is reconstructed, corresponding to the denoised signal. After the single value decomposition operation is provided, a single value decomposition is applied sequentially starting from a given window value. For each iteration, the root mean square value is calculated between a current and previous eigenvalue, calculating a minimum and its position of said root mean square value. The iterations are halted if the minimum is lower than a determined threshold value, otherwise increasing the window value and returning to the operation of decomposition of the acquired signal.

Abstract: Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.

Abstract: A driver device for driving a DC motor using PWM modulated drive signals includes comparator circuits for producing digitalized Back-EMF signals having first and second values as a function of the Back-EMF signals being above or below a respective threshold, and an inverter for driving the PWM modulated drive signals in a phased relationship with the digitalized Back-EMF signals. The driver device also includes controller circuits configured for controlling the respective threshold by minimizing the error between a time measured between two consecutive opposed edges of the digitalized Back-EMF signal and half a time measured between two consecutive homologous edges of the digitalized Back-EMF signal.

Abstract: A module for monitoring industrial processes for use in a system for monitoring industrial processes that comprises sensor means (7; 17) for detecting process quantities in a process station (20), acquisition means (8, 32; 32?; 32?) for acquiring measurement signals (R) issued by said sensor means (7; 17), processing means (9; 19) operating on signals (T; T1) generated by said acquisition means (8, 32; 32?; 32?) to obtain information on the quality of the process, and means for managing the production flow (9; 19), which operate on the basis of said information on the quality of the process and are located in a workstation (50) that is remote with respect to said process station, said monitoring module (30) being configured for being set locally at said at least one process station (20) for receiving measurement signals (R) issued by said sensor means (7; 17).