Patents by Inventor Giuseppe D'Eliseo
Giuseppe D'Eliseo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11132044Abstract: Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area, and an address of the first P2L data structure can be stored in the second P2L data structure.Type: GrantFiled: May 8, 2019Date of Patent: September 28, 2021Assignee: Micron Technology, Inc.Inventors: Giuseppe D'Eliseo, Xiangang Luo, Ting Luo, Jianmin Huang
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Publication number: 20210240633Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.Type: ApplicationFiled: April 19, 2021Publication date: August 5, 2021Inventors: Carminantonio Manganelli, Yoav Weinberg, Alberto Sassara, Paolo Papa, Luigi Esposito, Giuseppe D'Eliseo, Angelo Della Monica, Massimo Iaculo
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Publication number: 20210200672Abstract: Devices and techniques for corrupted storage portion recovery in a memory device are described herein. A failure event can be detected during a garbage collection operation on a collection of storage portions (e.g., pages) in a memory array. Here, members of the collection of storage portions are being moved from a former physical location to a new physical location by the garbage collection operation. A reference to a former physical location of a possibly corrupt storage portion in the collection of storage portions can be retrieved in response to the failure event. Here, the possibly corrupt storage portion has already been written to a new physical location as part of the garbage collection operation. The possibly corrupt storage portion can then be rewritten at the new physical location using data from the former physical location.Type: ApplicationFiled: December 29, 2020Publication date: July 1, 2021Inventors: Lalla Fatima Drissi, Giuseppe D'Eliseo, Paolo Papa, Massimo Iaculo, Carminantonio Manganelli
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Publication number: 20210182189Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: December 11, 2017Publication date: June 17, 2021Inventors: Xinghui Duan, Giuseppe D'Eliseo, Lalla Fatima Drissi, Giuseppe Ferrari, Eric Kwok Fung Yuen, Massimo laculo
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Publication number: 20210182207Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.Type: ApplicationFiled: December 13, 2019Publication date: June 17, 2021Inventors: Giuseppe D`Eliseo, Carminantonio Manganelli, Paolo Papa, Yoav Weinberg, Giuseppe Ferrari, Massimo Laculo, Lalla Fatima Drissi
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Patent number: 11023167Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.Type: GrantFiled: September 19, 2018Date of Patent: June 1, 2021Assignee: Micron Technology, Inc.Inventors: Giuseppe D'Eliseo, Graziano Mirichigni, Danilo Caraccio, Luca Porzio, Antonino Pollio
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Publication number: 20210141557Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.Type: ApplicationFiled: December 21, 2017Publication date: May 13, 2021Inventors: Eric Kwok Fung Yuen, Giuseppe Ferrari, Massimo Iaculo, Lalla Fatima Drissi, Xinghui Duan, Giuseppe D'Eliseo
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Patent number: 10983918Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.Type: GrantFiled: March 6, 2019Date of Patent: April 20, 2021Assignee: Micron Technology, Inc.Inventors: Carminantonio Manganelli, Yoav Weinberg, Alberto Sassara, Paolo Papa, Luigi Esposito, Giuseppe D'Eliseo, Angelo Della Monica, Massimo Iaculo
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Publication number: 20200356472Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: Zhao Cui, Eric Kwok Fung Yuen, Guanzhong Wang, Xinghui Duan, Giuseppe D'Eliseo, Giuseppe Ferrari
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Patent number: 10725904Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.Type: GrantFiled: December 13, 2017Date of Patent: July 28, 2020Assignee: Micron Technology, Inc.Inventors: Zhao Cui, Eric Kwok Fung Yuen, Guan Zhong Wang, Xinghui Duan, Giuseppe D'Eliseo, Giuseppe Ferrari
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Publication number: 20200226059Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.Type: ApplicationFiled: January 14, 2020Publication date: July 16, 2020Applicant: Micron Technology, Inc.Inventors: Giuseppe D'Eliseo, Luigi Esposito, Xinghui Duan, Lucia Santojanni, Massimo Iaculo
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Publication number: 20200210344Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.Type: ApplicationFiled: March 6, 2019Publication date: July 2, 2020Inventors: Carminantonio Manganelli, Yoav Weinberg, Alberto Sassara, Paolo Papa, Luigi Esposito, Giuseppe D'Eliseo, Angelo Della Monica, Massimo Iaculo
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Publication number: 20200142821Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.Type: ApplicationFiled: December 13, 2017Publication date: May 7, 2020Inventors: Zhao Cui, Eric Kwok Fung Yuen, Guan Zhong Wang, Xinghui Duan, Giuseppe D'Eliseo, Giuseppe Ferrari
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Patent number: 10552316Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.Type: GrantFiled: June 29, 2018Date of Patent: February 4, 2020Assignee: Micron Technology, Inc.Inventors: Giuseppe D'Eliseo, Luigi Esposito, Xinghui Duan, Lucia Santojanni, Massimo Iaculo
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Publication number: 20200004673Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Giuseppe D'Eliseo, Luigi Esposito, Xinghui Duan, Lucia Santojanni, Massimo Iaculo
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Publication number: 20190346902Abstract: Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area, and an address of the first P2L data structure can be stored in the second P2L data structure.Type: ApplicationFiled: May 8, 2019Publication date: November 14, 2019Inventors: Giuseppe D'Eliseo, Xiangang Luo, Ting Luo, Jianmin Huang
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Publication number: 20190018618Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.Type: ApplicationFiled: September 19, 2018Publication date: January 17, 2019Applicant: Micron Technology, Inc.Inventors: Giuseppe D'Eliseo, Graziano Mirichigni, Danilo Caraccio, Luca Porzio, Antonino Pollio
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Patent number: 10108372Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.Type: GrantFiled: January 26, 2015Date of Patent: October 23, 2018Assignee: Micron Technology, Inc.Inventors: Giuseppe D'Eliseo, Graziano Mirichigni, Danilo Caraccio, Luca Porzio, Antonino Pollio
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Patent number: 9183135Abstract: Subject matter disclosed herein relates to memory devices or accessing memory devices, and more particularly, but by way of example and not limitation, to preparation of a memory device to perform a memory access operation based at least partly on at least one indicator signal that indicates a memory access type.Type: GrantFiled: January 21, 2011Date of Patent: November 10, 2015Assignee: Micron Technology, Inc.Inventors: Massimo Iaculo, Ornella Vitale, Giuseppe D'Eliseo, Danilo Caraccio, Francesco Falanga, Emanuele Confalonieri
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Publication number: 20150212738Abstract: Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to a host. The memory is also configured to receive a plurality of memory access requests, a status request, and an execution command from the host, and to execute one or more of the plurality of memory access requests responsive to the execution command from the host. The execution command includes a plurality of respective indications that correspond to each respective memory access request of the plurality of memory access requests and that indicate whether the host is requesting the memory to execute each respective memory access request.Type: ApplicationFiled: January 26, 2015Publication date: July 30, 2015Inventors: GIUSEPPE D'ELISEO, Graziano Mirichigni, Danilo Caraccio, Luca Porzio, Antonino Pollio