Abstract: An integrated circuit chip which has a volatile memory also has a non-volatile memory for storing the parameter of a volatile memory which was measured while the chip was part of a completed wafer.

Abstract: A method and apparatus for recognizing a script written character wherein the character is entered using character entering means and digitised by appropriate means. The digitised character is then stored in, for example, a memory. Codes representing topological and vector features of the character are extracted from the character, then the topological and vector features of the character are compared with topological and vector features of a plurality of reference characters defining a set of reference characters stored in a memory. Each of the reference characters included in the set corresponds to a specific script written character. A logic process is then performed to determine which reference character of the set of reference characters has topological and vector features most closely corresponding to the topological and vector features of the digitized character thereby identifying the script written character.

Abstract: This invention relates to a method and apparatus for recognizing a script written character. The character is entered using character entering device and digitised by appropriate device. The digitised character is then stored in, for example, a memory. Codes representing topological, vector dimension features and the microfeatures of the character are extracted from the character, then the features of the character are compared with a set of reference features corresponding thereto stored in a memory. Each of the set of reference characters corresponding with a specific script written character. A logic process is then performed to determine which of the set of reference features most closely corresponds to the topological features of the digitized character thereby identifying the script written character. The relative weighting of the feature can be varied for different types of script or confusing characters to enable still more accurate recognition.

Abstract: Integrated circuit with a non-volatile variable resistor which is particularly adapted for use in a neuronic network. The integrated circuit comprises a symmetrically replicated structure including a floating gate MOS transistor (TRP; TRN) and an EEPROM memory cell based upon N-channel MOS transistors and including a read-out MOS transistor (TSP; TSN) and a tunnel-effect charge injection MOS element (TUNP; TUNN), with floating gates. The floating gates of all transistors and of the tunnel-effect element are connected together, with the ends of the resistor (R1P, R2P; R1N, R2N) being taken out from the source and drain regions of the floating gate MOS transistor.

Abstract: Circuitry and a method are provided for selectively switching a negative voltage (-V.sub.nn) to portions of CMOS integrated circuits, which circuitry comprises a switching/decoding matrix. The switching/decoding matrix comprises a control and decode logic (CDL) which controls signal VPPENABLE to control a positive charge pump (PCP) producing positive voltage (+V.sub.pp) and which further controls signal VNNENABLE to control a negative charge pump (NCP) producing said negative voltage (-V.sub.nn). The switching/decoding matrix further comprises, for each line to be switched, a switching module which comprises a PMOS transistor (PS) having its source connected to said line and its drain connected to receive said negative voltage (-V.sub.nn) produced by said negative charge pump (NCP). The PMOS transistor (PS) gate is driven by a drive circuit being in turn driven by said control and decode logic (CDL) and connected so as to receive the positive voltage (+V.sub.pp) provided by said positive charge pump (PCP).

Abstract: Data processing system implementing architecture of a neural network which is subject to a learning process, wherein the data processing system includes n.times.n synapses arranged in an array of j rows and i columns. A plurality of operational amplifiers respectively corresponding to the rows of the array are provided, with each operational amplifier defining a neuron. The input terminals of all of the synapses arranged in a respective column of the array are connected together and define n inputs of the neural network. The output terminals of the synapses arranged in a respective row of the array are connected together and serve as the inputs to a corresponding one of the plurality of operational amplifiers. Each synapse includes a capacitor connected between ground potential and the input terminal for weighting the synapse by storing a weighting voltage applied thereto. A random access memory has digitally stored voltage values for weighting all of the synapses.

Abstract: The subject of the invention is a learning system for a neural net physically insertable in the learning process, which comprises a detecting member for presenting to said neural net the basic information set that said neural net has to learn in order to provide a desired response; a microprocessor suitable to iteratively execute a learning algorithm based on a comparison among said basic information set itself, the response that the neural net provides and the response that one wants to obtain from the neural net (see FIG. 1).

Abstract: A read-only memory, comprising a decoder and a storage memory, wherein the decoder matrix and the storage memory matrix each comprises complementary metal oxide semiconductor transistors. Each column of the decoder matrix and each column of the storage memory matrix is connected to a single load or precharge transistor.